( ESNUG 470 Item 3 ) -------------------------------------------- [10/31/07]
Subject: ( ESNUG 468 #10 ) Arcadia Mustang, Tuscany DA, IC Compiler RP
> Arcadia moved into the design services realm, mostly "high performance
> CPU" consulting in Japan, and they stopped selling supporting Mustang.
> Their investors brought in Kah Yee Eg to be the new CEO to move them into
> an ASIC strategy. He's the former Synopsys Area Sales Director covering
> Asia Pac. From there he had several successful entrepreneurial ventures
> based in Singapore. Under Kah Yee, Arcadia changed its name to Key ASIC.
> Their business today is porting silicon IP for a Singapore fab. Wei-Kong
> Chia is the original CEO and founder of Arcadia, and I believe he is still
> active at Key ASIC.
>
> - [ The Invisible Man ]
From: Richard Bosenko <richard=user domain=daysman not calm>
Hi John,
Arcadia was purchased by Juniper Networks about 2000 or 2001. I believe
Mustang is still being used by the original Arcadia group, who repurchased
the product from Juniper, year before last. Mustang is currently being used
in conjunction with design service contracts by Arcadia. They are located
in Santa Cruz, California. I have spoken with several users and have been
told that Mustang has not advanced or been updated to meet many of the
current P&R design styles or requirements.
A customer savvy datapath technical contact is Matt Michels at Tuscany.
- Richard Bosenko
Tuscany DA Fort Collins, CO
---- ---- ---- ---- ---- ---- ----
From: Chi-Min Chu <chiminc=user domain=synopsys not calm>
Hi, John,
My guess is as good as anybody else's on where Arcadia is with Mustang,
but I can tell you that physical datapath capability in IC Compiler is
very much available. It provides a way to create regular structures
which specify the relative column and row positions for a group of
instances. We called the relative positioning of instances the Relative
Placement or RP constraints. During placement, the RP group is placed
as a single entity and optimization is done on the RP cells within the
context of the entire design. RP constraints are maintained throughout
placement, legalization, clock tree synthesis and routing phases. RP
supports both flat and hierarchical designs.
Here is an example to create a group named "designA::rp1", having six
columns and six rows:
# Create relative placement constraints
create_rp_group rp1 -design designA -columns 6-rows 6
# You can add leaf cells, other relative placement groups, and
# keepouts to relative placement groups using add_to_rp_group
add_to_rp_group designA::rp1 -leaf ...
add_to_rp_group designA::rp1 -keep ...
add_to_rp_group designA::rp1 -hierarchy ...
# Apply design constraints
read_sdc ...
# Read floorplan information
read_def ...
# Perform placement on the design
place_opt
# Preserve relative placement during clock tree synthesis
set_rp_group_options -cts_option fixed_placement [get_rp_groups *]
# Perform clock tree synthesis on the design
clock_opt
# Preserve relative placement during routing
set_rp_group_options -route_opt_option fixed_placement \
[get_rp_groups *]
# Perform routing
route_opt
RP increases predictability of results, reduces power and area. RP also
provides a method for maintaining structured placement for legacy or
intellectual property (IP) designs.
All IC Compiler users already have access to RP by default. If they want
to know more just RTFM (as in "Read The Fine Manual").
- Chi-Min Chu
Synopsys, Inc. Sunnyvale, CA
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