( ESNUG 487 Item 3 ) -------------------------------------------- [02/01/11]
From: [ We Need A King Solomon ]
Subject: We need one objective concise guide to all known assertion types
Hi, John,
Could your verification readers do me a favor and fill out any holes they
see in this table? Google searches have been a nightmare for this data.
IBM Sugar / IEEE 1850 PSL
Pros:
- Free, not controlled by any EDA vendor.
- Supported by Synopsys, Cadence, Mentor.
- Runs in Verilog, VHDL, SystemC and System Verilog source code.
- Multiple layers: Boolean, temporal, verification (vunit etc).
- You can easily hire engineers who already know these assertions.
Cons:
- Not all vendors support all flavors of PSL.
- VHDL-PSL is used widely as native to VHDL, but SVA is native
to System Verilog so most Verilog users choose SVA.
System Verilog SVA / IEEE 1800 SVA / OVM / UVM
Pros:
- Free, not controlled by any EDA vendor.
- Supported by Synopsys, Cadence, Mentor.
- Virtually identical capabilities as PSL. Identical semantics
for syntactically identical PSL properties.
- SVA standard is only for System Verilog but there exists
some non-standard SVA-binds-to-VHDL simulators.
- You can easily hire engineers who already know these assertions.
Cons:
- Only for System Verilog source. Some VHDL workarounds exist.
- Not all SVA constructs are supported across all vendors.
Cadence Verplex IAL / Accellera OVL
Pros:
- Supported by Cadence, Mentor, Atrenta, Zocalo.
- Runs in Verilog, VHDL, and System Verilog source code.
- Pre-defined modules for many commonly used assertions. Populated
with relevant coverage information.
- Uses standard SVA or PSL as the underlying implementation.
- Very simple to use, it is actually a piece of RTL code.
- You can hire engineers who already know these assertions.
Cons:
- Initially controlled by Cadence; now Accellera.
- Doesn't have the power of expression of PSL/SVA.
Mentor Questa QVL
Pros:
- Runs in Verilog and VHDL source code. (Unknown about SV.)
Cons:
- Controlled by Mentor.
- Only works with Mentor tools.
- You can hire a few engineers who already know these assertions.
Synopsys Vera OVA
Pros:
- Runs in Vera and some Verilog source code.
- Compatible with Vera legacy code.
Cons:
- Controlled by Synopsys. Being phased out to favor SVA/OVM/UVM.
- Only works with Synopsys tools.
- No integration with VHDL.
- Only around for legacy reasons.
- You can hire a few engineers who already know these assertions.
Mentor 0-In CheckerWare
Pros:
- Compatible with 0-In CheckerWare legacy code.
- Runs in Verilog and VHDL source code? (Unknown)
- Pre-defined modules for many commonly used assertions. Populated
with relevant coverage information.
Cons:
- Controlled by Mentor. Being phased out to favor SVA/OVM/UVM.
- Only works with Mentor tools.
- Only around for legacy reasons.
- You can hire a few engineers who already know these assertions.
Cadence Specman "e" / IEEE 1647 e
Pros:
- Compatible with Cadence Specman "e" legacy code.
Cons:
- Only supported by Cadence.
- Only works with Cadence tools.
- Only runs in Cadence Specman "e" source code.
- You can hire a few engineers who already know these assertions.
SystemC Assertions
Pros:
- Can be used in a SystemC testbench.
Cons:
- Not supported by major EDA vendors yet. JEDA has one tool.
- Only works in SystemC source code.
- Does not have the support for compact temporal specification and
requires manual (error prone) modeling of temporal behavior.
- You can't hire any engineers who already know these assertions.
JEDA Assertions
Pros:
- Runs in Verilog and VHDL source code? (Unknown)
Cons:
- Controlled by JEDA Technologies.
- Only works with JEDA tools.
- You can't hire any engineers who already know these assertions.
VHDL Assertions
Pros:
- Free, not controlled by any EDA vendor.
- Does not require knowledge of any additional property language.
- Compatible with VHDL legacy code.
Cons:
- Works only in VHDL source code.
- Limited to basic combinational assertion. Requires extensive
temporal modeling to check complex functionality. Not scalable.
- Why model assertions in VHDL when PSL is in the VHDL standard?
- You can hire a few engineers who already know these assertions.
Homegrown Assertions:
Pros:
- Free, not controlled by any EDA vendor.
- Runs in Verilog, VHDL, System Verilog, whatever you make it run in.
- You can have a company specific methodology around your assertions.
Cons:
- Non-standard, non-portable.
- Needs dedicated team to develop/maintain co's assertion lib.
- You must teach each new engineer how to do your co's assertions.
- You can't hire any engineers who already know your co's assertions.
My verification group is in chaos about which assertions to use and which
to avoid. Each engineer seems to favor a conflicting set of assertions.
We don't want to use all of them. It would be an untenable long term
maintenance nightmare. We're hoping that the verification engineers not
from our company could fill out the PROs and CONs that we're missing for
each flavor of assertion so we can settle on only one or two of them.
Thanks in advance.
- [ We Need A King Solomon ]
P.S. Asking the major EDA vendors didn't help; they each only recommended
the specific assertions that their current tools support.
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Editor's Note: If you have input for this, please email directly and
I'll add whatever changes/additions on this specific web page. - John
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Editor's Note: Latest edits to this page were on Feb. 2, 2011. - John
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