( ESNUG 488 Item 7 ) -------------------------------------------- [03/25/11]
From: Trent McConaghy <trentmc=user domain=solidodesign not mom>
Subject: An analog engineer's Trip Report of DATE 2011 in Grenoble, France
Hi, John,
Last week (March 14-18) was DATE 2011, at Grenoble in the French Alps.
DATE (Design, Automation, and Test Europe) is Europe's largest EDA con; it's
the DAC of Europe, if you will.
This was the first DATE in Grenoble. DATE now alternates between Grenoble
and Dresden, reflecting a shift in Europe: Grenoble employs 38,000 people in
semiconductors.
DATE'11 has both an academic program and a trade floor show.
This year at DATE'11 there were:
- 199 presentations, 12 industrial papers, and 82 interactive
presentations, grouped into 77 sessions.
- There were 781 submitted papers, including 355 from Europe (55%),
220 from North America, and 175 from Asia. About 300 Technical
Program Committee members did a total of 4,000 reviews, and 211
papers were accepted.
Around 70 mostly small European companies exhibited in the trade floor show.
This number exceeded expectations; additional space had to be found for a
second smaller hall. Oddly, none of the big EDA vendors (Cadence, Synopsys,
Mentor, Magma, Apache) had a booth at DATE'11. Mentor did hold a special
lunch & learn, and some had smallish displays in the Global Foundries booth.
Booth traffic was strongest on Monday, and tapered off. Visitors on the
trade show floor were predominantly academics, but some customers, too.
Interesting data:
Geerd Teepe (Director Design Enablement, Global Foundries):
- Design costs $60 M for 45 nm, $90 M for 32 nm, and $120 M for 22 nm.
- By 2020, foundries' share of semi revenue will rise to 66%.
- Global Foundries has increased R&D spending to 18% of revenue.
Maria Marced (President, TSMC Europe):
- 65 nm 2006, 40 nm 2008, 28 nm 2010, 20 nm ..., down to 7-8 nm via
a "difficult but clear" path.
- TSMC had 3x more tapeouts (78) at 28 nm vs. 40 nm; which of course
is opposite of the usual assumption that the number of design starts
per node decreases.
- For projected cost reductions of 30%, TSMC is going from 300 mm to
450 mm wafers in 2012-2014 (pilot), 2015-2016 (production 20 nm/14 nm),
and nothing but 450 mm after 2016.
- Reflecting the innovation needed to scale, TSMC doubled its R&D budget
over the last 2 years.
Philippe Magarshack (GM of Central CAD and Design Solutions, ST):
- Semi CAGR moving from 15% to 7%. Key growth areas are wireless (8.9%)
and automotive (8.2%).
- For TV chips, ST is/will be on 40 nm 2008-2011 (including a bifurcation
of power supply to low/high Vdd); 32/28 nm 2009-2015 (adding SIP here);
and 20 nm in 2012-2017 (adding 3-D here, photonics on horizon too).
- By 22 nm, he predicted just 3 IDMs left: Intel, Samsung, and ST.
- ST has active research down to 8 nm.
Rudy Lauwereins (VP Smart Systems Technology, IMEC):
- Until 130 nm, 2 generations of scaling would give 4x less power and
4x more functionality.
- But since 130 nm, Vdd cannot shrink as fast: 2 generations gives
just 1.4x less power and therefore 1.4x more functionality (assuming
a constant power budget).
- Scaling Vdd is only possible with great engineering efforts: high-K,
then Ge-III/IV, then Tunnel FETs; but these are "too little, too late".
- Unrelated datapoint: transistors now cost under $1 n!
Antun Domic (Sr. VP & GM, Synopsys):
- EDA companies spend 30% of revenue on R&D, compared to (traditionally)
~15% for semis and fabs.
- Challenges include double patterning (DPT), complexity, 3-D, low power,
and analog/mixed-signal.
On Variation:
Variability was definitely a hot topic at DATE; there were many papers,
sessions, panels, tutorials etc. on it. Summed up by Maria Marced (TSMC):
"variability is the main design challenge." Process variation is a big
problem that exists today. For example:
- Sani Nassif (IBM):
It affects SRAMs today, latches tomorrow, and then inverters.
(Everyone should worry when variation hits inverters, because that
represents all of digital logic.)
-Jean-Paul Morin (ST), Philippe Raynaud (Mentor), Vincent Fischer
(Infiniscale), and myself (Solido) were in a panel discussing the
pros and cons of approaches and tools to handle random process
variation and other variability that are in industrial use. There's
fast Monte Carlo + real statistical corners at one extreme, RSM
(response surface modeling) at the other, and many mixtures in between.
Multiple speakers described research in improving reliability (transistor
aging) models and quantifying the effects. Speakers included Georges Gielen
and Elie Maricau (KU Leuven), Yu Cao (Arizona), and Asen Asenov (U Glasgow,
GSS). We've had HCI (hot carrier injection) for 25 years and NBTI (Negative
Bias Temperature Instability) for 5 years; but they are becoming much worse
at 32nm and below and on high-k gates, and they are becoming stochastic
because the devices are small enough for particles are now countable.
In addition there are new effects, including PBTI (Positive Bias Temperature
Instability), and Soft Breakdown (SBD). Note that the EDA Big 3 support a
degree of reliability simulation, though not typically with the most
up-to-date models: Synopsys Hspice MOSRA, Cadence RelXpert (from BERT), and
Mentor Eldo user-defined reliability modeling.
Aging on wires = electromigration. Mean-time-to-failure ("mean") is staying
about the same, but the standard deviation is increasing, and is starting
to matter (Nassif).
Other variability is not going away, and in some cases also getting worse:
environmental variation (Vdd, load, temperature), noise, EM, parasitics,
layout-dependent effects, and more. Technology innovations can lead to
variation issues, like stress (Nassif), and 3-D (Lauwereins).
- Trent McConaghy
Solido Design Automation Saskatoon, SK, Canada
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