( ESNUG 491 Item 3 ) -------------------------------------------- [04/14/11]
Subject: San Jose SNUG 2011 Trip Report with Aart's keynote, HSPICE, HSIM
From: John Busco <jbusco=user domain=nvidia not mom>
Hi John,
SNUG San Jose 2011 just wrapped up and, as Chair of the Technical Committee,
I'd like to share a recap with ESNUG readers.
It was the biggest SNUG ever! The 2,375 attendees was a 10% increase over
last year's 2,070 attendance. Aart gave a global overview of the electronics
industry, and how it impacts chip designers -- consumer electronics driving
most of the growth, pressure to get to market first, you must integrate a
wide array of IP into chips, and you can only use the same or less power.
The attendees voted these Best Paper Awards:
First Place - Phil Simpson & Jennifer Stephenson - Altera
"Creating Reusable Design Blocks Targeting FPGA Devices."
Second Place - Richard Bishop - AMD
"A Case for Adopting Galaxy Constraint Analyzer."
Third Place - Bob Turner - Broadcom & Nish Balaji - Synopsys
"Implementing ARM Cortex A9 using Synopsys Physical Guidance."
Tech Committee Award - Alexander Tetelbaum & Rich Laubhan - LSI with
David Keyser - Synopsys, "Advanced OCV Timing Derating Experience"
Aart's big announcement was "DC Explorer" which does synthesis ~5X faster
than regular DC and gets results within 10% of the real thing. He also gave
the case for customers using a cloud computing service bundling servers with
EDA licenses.
The first night, the Designer Community Expo had 60 companies exhibiting.
The second night, 700 users played air hockey in beer gardens during the
German-themed "SNUGtoberfest".
- John Busco
Nvidia Corp. Santa Clara, CA
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From: Nigel Bleasdale <&nbleasdale=user domain=solidodesign not mom>
Hi John,
I attended this year's Synopsys User Group (SNUG'11) event in San Jose on
March 28. This was the 21st SNUG, but my first time attending it.
AART DE GEUS' KEYNOTE: "FAST FORWARD"
- Aart started with the humbling experience from the tragic disaster that
hit Japan to which he expressed SNPS's "shared sense of participation."
- To illustrate the theme of the conference (Fast Forward) and driving a
vision past current expectations, he discussed technology such as Watson
passing a new milestone in AI, the first synthesis of DNA into a living
microbe, and the shift in thinking after the release of the iPad.
- We must create differentiation, by being better, sooner, or cheaper.
Said EDA can follow the cycle of: Model - Verify - Improve.
- There is a huge push to "smart everything." Everything will talk to
everything else through the Internet, requiring huge amounts of data
exchange, security and increased standardization. Smart requires an
understanding of things in their context. The big picture:
Smart ->Common Sense ->Seeing
- Systemic Complexity. With the addition of a lot of smart objects all
connected together, Systemic Complexity is interdependence where any
weak link leads to a failed technology or ineffective supply chain.
The whole is no longer the sum of all the parts, but the product of
all the parts.
- Synopsys' vision on Quality, Standardization and IP collateral.
- Aart's Synopsys technology highlights in his speech:
1. Verification standards are important; said Synopsys has the fastest
execution to standards UVM, OVM and VMM.
2. Improved execution in design and debugging with partial compilation.
3. Finding the right test vector set for coverage.
4. A capability to understand 'X' state propagation.
5. Expanded equivalence checking.
6. Announced DC Explorer for early RTL development. Said it can run
with incomplete data and 10% correlation at 5x runtime.
7. HSPICE has been going through some dramatic improvements over the
past year with "significant" performance gains in performance on
different hardware configurations.
8. Synopsys is looking at cloud computing. Design cycle demanding
verification peaks are hitting the bandwidth limits of available
hardware (or licenses). This creates an opportunity to rent
virtually unlimited resources on the cloud for a short period of
time. Is currently exploring this with VCS and potentially HSPICE
in the future.
9. Synopsys has expanded its IP portfolio, with the addition of memory.
Aart said that Synopsys runs 10X the verification on their IP compared to
what is typically done. Their IP group has over 700 engineers with 450
analog/MS engineers designing with all-Synopsys tools. About 30% of $$$
spent is on R&D with 15%+ in acquiring new technologies. Invests in TCAD
and optical modeling.
CUSTOM DESIGNER TUTORIAL
by Marc Swinnen and Frederik Ivarsson
As a former Cadence employee in custom, I was especially interested in the
progress Custom Designer has made. Some notable takeaways:
- The schematics use interactive editing and docked assistants that are
familiar to Virtuoso IC 6.1 users.
- Design-Rule-Driven modes for layout.
* "Visual Only" non-invasive and simply highlights when violations
occur.
* "Enforce" will try and enforce a rule that is about to be violated,
but can be overridden by 'pushing' past it.
* If violations exist, then "Autofix" can be used to correct violations
over any area selected.
- Covered Shadowing, auto-abutment, cloning, and auto-via-array insertion
on power rails. Flight-lines can have jogs to make them easier to see.
- Routing is interactive, with point-to-point, and can also be done simply
by following the cursor.
- Auto-complete is available and full net routing with the ability to set
'way points' to hint on the preferred path. All routing automatically
follows the preferred routing rules.
- Designs are visible between IC Compiler and Custom Designer.
- Extraction through StarRC is saved directly to Open Access and
annotations are easy to see on schematic or layout views.
- IR and EM analysis is also available based on the StarRC results and
visualized back in Custom Designer.
- Nanotime is integrated for transistor level STA and can be used to
generate .lib timing models.
- All Synopsys' 450 analog/MS designers in the IP group use Custom
Designer on 180 nm to 28 nm blocks.
28nm MOSFET AGING MODELING & SIMULATION USING HSPICE & HSIM MOSRA
by Liping Li of Altera
- Liping introduced the two main mechanisms that influence aging: BTI and
HCI. NBTI and PBTI exist for HK metal gate and NBTI only on SiON. HCI
increases on all devices as geometries shrink.
- Differing reliability model technologies. Other methods rely on current
sources to model the degradation over time. This method has been around
for many years, but this capability was not readily available to HSPICE
user.
- Synopsys developed MOSRA using a physics approach they say is more
integrated and more scalable.
- In his testing results, Liping showed the model accurately fit the
recovery in BTI with accurate modeling of the trapping and detrapping
time constants. The model integrates well the response over transient
stresses during simulation. Liping's findings:
* MOSRA Isub is more accurate than Isub in BSIM4.
* Using MOSRA is a two-step process with a fresh sim followed by the
post stress sim.
* With two examples, Liping showed the delay change in routing paths
for an FPGA. A fast change initially and then slows to a log
timescale. For an I/O, he showed that the rate of degradation
increased at lower temperature and higher operating frequency.
DESIGNER COMMUNITY EXPO
Monday evening was well attended, with 600+ people staying late to visit
the 60 Synopsys partners presenting their wares. I was representing
Solido, demonstrating our variation tools for custom IC design. It was
good to talk to other partners as well as the conference attendees.
Over the three days this SNUG had 2,375 attendees.
- Nigel Bleasdale
Solido Design Automation San Jose, CA
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