( ESNUG 492 Item 5 ) -------------------------------------------- [05/26/11]
From: Jun Chen <chenjunic=user domain=huawei got calm>
Subject: A custom engineer's 65 nm benchmark of Solido PVT+ and Monte Carlo+
Hi, John,
We used Solido Variation Designer PVT+ and Monte Carlo+ packages to help us
find and fix variation bugs for our custom IC designs.
Solido works with Cadence Virtuoso ADE/Spectre/APS, Synopsys HSPICE/HSIM,
Magma FineSim and Berkeley AFS. Of these, we have used Solido with Cadence
Virtuoso ADE/Spectre/APS.
Before we bought Solido, we did a detailed eval on multiple circuits. Our
general evaluation criteria were:
- Reduce our PVT corner analysis runtimes
- Reduce our Monte Carlo runtimes
- Reduce our effort to analyze results and debug for variation
Below are our eval benchmark results. The designs were in TSMC 65 nm.
TEST 1: OP AMP
To test our Op Amp, we set up a Cadence ADE, Spectre, APS, with Solido
PVT+ and MC+. For PVT+, we used 2 Spectre and 2 APS licenses with
Solido, and for MC+ we used 12 Spectre and 12 APS licenses with Solido.
1. PVT+ Analysis. 45 comb of corners (5 process x 3 voltage x 3 temp)
Each corner took approximately 1-3 seconds to simulate with Spectre.
We used Solido's PVT+ design-of-experiments to narrow the 45 corners to our
8 worst corners. This took 45 x ~2 seconds, or 1.5 minutes total. We ran
the design on those 8 corners and our spec failed on 4 of them.
2. Debug. Solido's sensitivity analysis suggested fixes to adjust two
transistor lengths. After making the changes, we re-ran the simulations
across the 4 failing corners. The design now passed spec.
3. Verify. We ran a final check with Solido PVT+ across all 45 corners.
It passed specs at all the corner conditions.
We then used Solido MC+, specifically to understand the impact of random
variation on 3-sigma yield.
1. MC+ Analysis
Step 1. Theoretically, depending on the sigma yield we want, the
average number of Monte Carlo simulations varies:
1 sigma: ~15 simulations
2 sigma: ~150 simulations
3 sigma: ~3000 simulations
4 sigma: ~500,000 simulations
5 sigma: ~50,000,000 simulations
6 sigma: ~5,000,000,000 simulations
Since we design to 3-sigma yield for these circuits, a typical Monte
Carlo run in a simulator would take about 3000 simulations. The time
needed would vary depending on the multi-core processing we use. For
example, a single core simulation takes 2 seconds per simulation, or
1 hour 40 minutes total, but a 2-core simulation would take 50 minutes,
and a 4-core simulation would take 25 minutes.
In contrast, Solido MC+ was able to show that our op amp failed to meet
our 3-sigma yield spec in only 40 simulations, or 1 min 20 seconds
(using one core). MC+ does a real-time analysis as the Spectre
simulations run, and identified sufficient failures after the first 40
simulations to determine the circuit would never meet the yield target.
This was a 75x time savings.
In our previous flow, we could not begin debugging our design until
after the simulations were complete, so being able to find that design
was failing to meet the yield spec in only 1 min 20 seconds was very
useful.
Step 2. Since our MC+ analysis determined we were failing our 3-sigma
spec, we used the Solido MC+ feature that extracts 3-sigma statistical
corners. This took Solido 200 simulations at 2 sec each, or about 6
minutes 40 seconds. Solido MC+ extracted two statistical corners, one
for each of our specs.
2. Debug. We used Solido's sensitivity analysis to help us debug our op
amp. Using the two extracted statistical corners, Solido automatically
identified two transistor lengths for us to modify. Normally we would
have had to go through repeated manual Monte Carlo analysis to find the
sensitive devices and determine what fixes might work. This step alone
would have taken 10,000's simulations, but we were able to do it with
Solido in 100's simulations.
3. Verification. After modifying the transistor lengths to fix the design
at the statistical corners, we did a final verification run. You can
specify the sigma-level they want in Solido MC+ up to 7 sigma. We
selected 3-sigma. Instead of the typical 3,000 simulations, it took
Solido MC+ only 1,500 simulations to determine that the circuit met our
3-sigma yield target (because enough samples passed).
TEST 2: Digital-to-Analog Converter (DAC)
We wanted to measure the non-linearity of our DAC circuit to 3-sigma
parametric yield using Solido Monte Carlo+ with ADE/Spectre.
1. Analysis
The non-linearity spec took about 30 minutes per simulation. To measure
non-linearity at 3-sigma, 3,000 simulations * 30 min/sim = 1,500 hours
would have not been possible.
Because Solido Monte Carlo+ can extract the statistical corners, we used
a fast running spec that only took 1-2 seconds per simulation to extract
3-sigma statistical corners. From our experience, we knew that this fast-
running spec was correlated to the non-linearity spec, so we could rely on
the results. Solido provided 2 extracted corners from the 3-sigma (99.73%)
boundary of the Monte Carlo-sampled distribution. We then used these 2
extracted corners to simulate the non-linearity of our DAC at 3-sigma. If
the non-linearity of the extracted samples met the specification, then the
design will have 99.73% yield. This took 2 sims x 30 min/sim = 1 hour.
The simulations produced a waveform which we used to measure the
non-linearity and confirmed that it met specification. We added this
measurement of non-linearity at 3-sigma in our design documentation.
Solido made measuring non-linearity at 3-sigma practical.
The table below summarizes our benchmark highlights.
Op amp DAC
------ -------------
MC+ initial sims required 40 n/a
(75x savings)
# of statistical corners extracted 2 2
# of devices fixed 2 n/a
MC+ sims for final verification 1,500 2
(2x savings) (not feasible w/o Solido)
Problems I saw during the evaluation:
1. When we re-ran a simulation in Solido, it was done in the foreground
preventing other work while the simulation runs. For simulation
times that are long, it can affect us from doing other work while
waiting for the simulations to finish. Solido has now fixed this
problem letting the simulations run in the background in their latest
2.5 release.
2. Some of the simulations in Solido first showed a status of "Done" and
then changed to "Interrupted." This bug was fixed in their latest
v2.5 release.
I liked its 'Fractional Factorial' Design-of-Experiment to do the first step
PVT analysis very quickly. It saved me a lot of time in iterations. It
focuses on the most likely causes of failures to narrow the number of
corners.
Also, compared to Cadence 5.1.41 which can only run corners on single-core,
Solido can run corners on multi-core and saves lots of simulation time.
We now use them for our variation-aware custom flow for both AMS and RF
projects, both here in Shenzhen and at our Shanghai design center.
- Jun Chen
Huawei-HiSilicon Shenzhen, China
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