( ESNUG 492 Item 10 ) ------------------------------------------- [09/20/11]
From: Ting Ku <tku=user domain=nvidia got calm>
Subject: NVidia on Solido Variation Designer with SNPS HSPICE for 6-sigma
Hi, John,
My company purchased Solido Variation Designer in July 2011 and have been
using it on our 28 nm designs, with future plans to use it as we migrate
to 20 nm. We use Solido on our simulation farm of 100's of Synopsys HSPICE
licenses to do production designs like embedded memory, FF's, and PLLs.
The three Solido Variation Designer tools below help us identify if our
circuit passes or fails, finding the sensitive devices and suggesting fixes.
1. Solido High-Sigma Monte Carlo+ (HSMC)
High-Sigma analysis is critical for cell functions that are
instantiated 1000's of times. Solido High-Sigma Monte Carlo sampling
selects the high-sigma samples using Solido's proprietary approach,
and then simulates using HSPICE.
2. Solido Monte Carlo (MC+)
MC+ uses a smarter sampling method than random Monte Carlo. It uses
Optimal Spread Sampling (OSS), which evenly distributes the samples,
so you can obtain more accurate results with fewer samples. Monte
Carlo+ also includes dynamic stopping conditions, which automatically
run the optimal number of samples to verify to the target yield or
sigma.
3. Solido PVT+
PVT+ is an adaptive corner case evaluation algorithm, which is useful
for our system-level signal integrity simulation.
MONTE CARLO COMPARISONS: # OF SIMULATIONS & SIMULATION TIME
Traditional (default) Monte Carlo sampling for Synopsys HSPICE is purely
random, with no optimization to reduce the number of simulations. It is not
feasible to do high-sigma designs this way. So instead we use HSPICE with
Solido High-Sigma Monte Carlo.
CASE 1: 6-Sigma Flip Flop
Tool # of Simulations Simulation Time
------------------ ----------------- ---------------
HSPICE Monte Carlo 5 billion samples 6 months*
Solido HSMC with HSPICE 4000 samples 12 hours**
* Estimate based on a 0.6+ sec time for each simulation using a 200
HSPICE license simulator farm. We didn't actually run this, because
it would have taken too long to complete.
** This includes 6 hours for the host engine to do the high-sigma
sample generation and selection and 6 hours of simulation time.
It only takes us about 30 minutes to set up Solido.
CASE 2: 4-Sigma Flip Flop
Tool # of Simulations Simulation Time
------------------ ---------------- ---------------
HSPICE Monte Carlo 1 million 3 days
Solido MC+ with HSPICE < 2000 3 hours
Solido's recommended threshold for # of variables you can have for HSMC is
1000. NVIDIA's usage confirms that it scales to 1000 variables just fine.
For circuits where we need substantially more than 1000 variables, our
workaround is to hand-pick transistors of interest to limit the number of
variables to 1000. Solution-wise this works; however, I would like to see
Solido add enhancements to help us select devices, as the process is tedious
when we have 20,000 to 30,000 variables. For example, I would like to be
able to save the selections and have the selections to be automated, where
we can click on the transistor in each netlist individually.
Even so, we wouldn't be able to do this at all with random Monte Carlo. It
can't even pay the cover charge.
PARALLELIZATION
We ran Solido on our simulation cluster with a large number of Synopsys
HSPICE licenses. I've run hundreds of Synopsys HSPICE licenses concurrently
with Solido as well as without it.
We must be able to do this kind of concurrent run with Solido to scale its
variation analysis to meet our needs.
The smallest # of Solido Variation Designer simulations we run is 2,000.
Case Time/run Runs Total time
---- -------- ---- ----------
PLL 20 min/run 2000 3.3 hours using 200 simulator licenses
Flip flop 30 sec/run 2000 5 minutes using 200 simulator licenses
TIP: The host operation in Solido's Variation Designer is highly
dependent on the server latency. We get the best results by
running it on a local host machine.
TIP: The best method is to launch Variation Designer from a shell
window, rather than launching it to a cluster management system,
then let Solido distribute the simulation jobs to the cluster.
This gives noticeable performance improvement, perhaps 20% faster.
E.g. 8 minutes versus 10 minutes.
Solido High-Sigma Monte Carlo does two main things:
1. First, it generates and selects high-sigma samples, which is not
currently parallelizable.
2. It simulates samples, which can be parallelized, as discussed above.
The current time required for Variation Designer to do both #1 and #2 is
about evenly split. However, the time required for #1 could be shortened if
it was parallelizable. Solido claims this will occur in its v2.7 release in
November. In the meantime, we have found that #1 runs faster if we run
Solido on a dedicated computer, as opposed to a shared machine.
SOLIDO SELF-VERIFICATION / ACCURACY
Solido High-Sigma Monte Carlo self-verifies its high-sigma predictions
during runtime using SPICE simulations, and then adapts its behavior to
increase its accuracy as needed based on the results.
We also did a brute-force verification of HSMC against Monte Carlo for our
embedded memory design. Solido's HSMC agreed with our millions of runs of
traditional Monte Carlo. When we used Solido's High-Sigma Monte Carlo for
our 5 or 6 sigma designs, we caught way more failures because brute force
Monte Carlo couldn't do it.
Solido generates and selects true Monte Carlo samples (SPICE accurate).
They do not use an artificially constructed worst case, these are real
failure cases. We could ultimately do silicon correlation to verify but
such effort would need a lot of samples and take an excessive amount of
time. We rely on High-Sigma Monte Carlo since it is more practical.
METHODOLOGY WITH SOLIDO HIGH-SIGMA MONTE CARLO & HSPICE
Before using Solido, we ran 2 -2.5 sigma, assumed a Gaussian distribution,
and did a simple linear extrapolation to determine the results at a higher
sigma. This approach gave us extremely inaccurate results -- in most cases,
results were very pessimistic.
Below is the process we now use with Solido to meet our design spec and
parametric yield goals for High-Sigma designs.
1. We identify the corners on which to run Monte Carlo. For system
design, we use Solido's fast PVT, which uses design of experiments,
regression and an adaptive algorithm to accurately and quickly
identify the worst-case corners.
2. One of our analog engineers does a first rough cut to identify
sensitive devices by experience and design intuition. We assume that
the "designer intuition" is pessimistic. He or she asks for analysis
on more devices than is necessary.
3. We then run Monte Carlo+ or High-Sigma Monte Carlo+ for a sensitivity
plot to zero in on the sensitive devices. If the circuit doesn't
pass, we look at Solido's plots and decide which devices to tweak.
4. We rerun the flow above to verify our fix.
Our 3-Sigma Design methodology with Solido MC+ is fundamentally the same
workflow as for a high-sigma design, with the same "before and after".
SOLIDO FAST PVT & POWER CHARACTERIZATION
Solido's Fast PVT comes into play when we identify the corners on which to
run Solido Monte Carlo+ or Solido High-Sigma Monte Carlo+.
In the circuit world, doing a brute force run of all exhaustive permutations
and look at the results is not so bad because the variables are limited to
Temperature, Process and Voltage. For a circuit design, we usually have
fewer than 10 corners.
However, if you step outside to the system design world, you need to
consider not just silicon variation (PVT) but also package variation, board
variation, and other design team members' components, i.e. it increases
exponentially. For system design, we typically have a few thousand corners.
Power characterization. By leveraging Solido's Fast PVT technology, we
created a new application for power that leverages Solido's Fast PVT
technology. When characterizing our power mode scenarios, each cell has a
different condition and power dissipation signature. Unfortunately, brute
forcing it would require 200,000 entries. Solido Fast PVT generates a model
to figure out the trend of statistical data, which is used to fill in the
trend between the sample points. So far we have been able to use Solido's
solution in a highly automated brute force way to finish 14K simulations in
one day without much manual effort.
Solido PVT replaced our earlier SAS JMP tool for our LSI designs. JMP does
some statistical analysis, but is not integrated; our simulation data had to
be manually entered. Additionally JMP doesn't do cell verification.
DEPLOYMENT OF SOLIDO HSMC & MC+
Solido High-Sigma Monte Carlo+ and Monte Carlo+ enables us to do variation
analysis on a number of applications that wouldn't otherwise be feasible:
1. Memory Designs
Our first deployment was to apply Solido's High-Sigma Monte Carlo to
our memory design like SRAM bit cell and sense amp design. High-
Sigma analysis is required for chips that are duplicated 100s and
thousands of times.
2. Standard Cell Library Designs
Analyze set up and hold time for flip flops. We want to design the
flip flops to statistically guarantee set up and hold times.
3. Analog/mixed-signal/RF Designs
Analyze PLL's to 3-sigma and if circuit doesn't work identify
sensitive devices to tweak and verify fixes.
4. Porting architectures to different process nodes
After we port a design, we need to do variation analysis to tune the
design to accommodate the variation for the new process node.
Variation Designer is well-designed, and easy for our designers to pick up
because it has a friendly GUI with intuitive buttons. The entry point is a
SPICE deck that our designers know and love. It's also constructed to be
modular, expandable and linkable. No one has a crystal ball, so instead of
a specific tool we need something adaptable and accommodates adjustable
workflows.
We have definitely identified problem devices in Solido runs, such as
problem corners. Either we pass our Defect Density per Million (DDPPM)
goals, or we make fixes.
Regards,
- Ting Ku
NVidia Corp. Santa Clara, CA
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