( ESNUG 494 Item 1 ) -------------------------------------------- [10/20/11]
From: [ Mighty Mouse ]
Subject: Aart's Boston keynote pushes an All-SNPS flow and TLMcentral.com
Hi, John,
Please keep me anonymous.
I was able to attend Aart's Boston SNUG keynote on 9/29/11 and I wanted to
pass on my notes to your readers.
Aart's speech was similar to others that I've seen him give but with some
fresh content. My guess is ~250 to ~300 people in attendance.
Usual market data showing trends, downturns, etc.
- The economy is in tough shape (really?)
- His graphics were actually very nice and told a good story but
his message difficult to capture.
Aart said it is no longer good enough to sum up unique values for each
stage of a best-in-class EDA tool flow.
- Sum != Product (by product he means if any one of the inputs
is a 0 then the output is a 0).
- He pitched for why a total Synopsys toolset is more valuable than
best-in-class EDA tools. Typical SNPS sales talk.
Design must include top-down and bottom-up design. People battle over this
religion but both must exist.
- Used a diagram with two triangles showing this concept but I can't
completely remember the picture he drew.
He rehashed Design Explorer as a "new" tool (to compete against Oasys.) It
uses incomplete information and gets within 10% timing at 5-10x speed.
- Spent some time talking about look ahead technologies. For example,
logic synth now has a some P&R capability to make smarter decisions.
- Claims that [most] all SNPS tools do stuff like that now.
In the Transistor -> Gate -> RTL -> SoC progression Aart pitched his IP as
the key from RTL to SoC.
No talk of ESL -- I guess he doesn't know what it means either.
Talked a lot about IP and the value that it provides to designers. I think
he conveniently skipped the point that IP is hard to integrate and to
validate that it does exactly what we want.
System Level Design
- Talked about SNPS System Level tools and a "new" tool called Virtualizer
that merges CoWare, Virtio and VaST. (This was announced after DAC.)
- This is high-level virtual system prototyping stuff. "Models are
critical. Synopsys has most of the high-value models because of
various acquisitions."
- Showed the old Synplify HAPS for prototyping hardware.
Announced a new partnership with ARM to supply ARM Cortex Fast models. This
is evidently different than the ARM models that Carbon provides (which are
RTL converted to C/SystemC?).
TLM Central (TLMcentral.com)
- Announced this at the show. It's a new database or repository of sorts
for transaction-level-model IP.
- Supposedly it's "open" for anyone to participate.
- I think the idea is that vendors can put up models, datasheets, or
other IP and information for free exchange.
- Sponsors are: ARM, Carbon, Doulos, Forte, HCL, IMEC, Imperas, ITRI,
LSI, MIPS, OCP-IP, OSCI, Ricoh, Sonics, Tensilica
We'll have to see what value this brings to the industry, if any.
Synopsys USB 3.0 DW
- Aart touted their USB 3.0 DW. There may have been a press releases
on this, too.
- 10x faster than USB 2.0, 30 designs in progress, 20 logos, 9 tapeouts
Aart was his usual self, funny and clever. His presentation took 75 minutes
and another 15 for Q&A. No interesting questions really.
- [ Mighty Mouse ]
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