( ESNUG 495 Item 4 ) -------------------------------------------- [11/11/11]
Subject: A second set of Berkeley AFS vs. Cadence Spectre/APS benchmarks
> There were 840 total elements, 10 MHz clock frequency, oversampling ratio
> of 500, .18 nm technology. All simulators/simulations were run using a
> Quad core Xeon, with 12 GB of memory.
>
> Time (hrs:min) SNDR (dB) Speed-up
> Cadence Spectre 101:27 108.8 1.0
> Cadence APS (n=4) 20:15 111.0 5.0x
> BDA AFS 5:50 114.7 17.4x
> BDA AFS MT (n=4) 3:50 114.8 26.4x
>
> Cadence Spectre took over 100 hours, and Cadence APS cut down that sim
> time by a factor of ~5X with 4 cores. BDA AFS cut it down by 17X, and
> with 4 cores. The AFS simulation time was under 4 hours for 26X.
>
> - from http://www.deepchip.com/items/0494-09.html
From: [ Speedy Gonzales ]
Hi, John,
I thought your readers would like to see the second BDA AFS vs Spectre user
benchmark I saw at TechMart. Again, I am keeping the user and his company
'anonymous' since he shared hard data that might anger Cadence.
Please keep me anonymous, too.
Circuit #1: Bandgap; PTAT; Bias; 6b DAC, comparator and SAR logic
2194 elements: bjt 3, mos 995, capacitors. 356
Runtime Speed-up
Spectre 198 min 1x
BDA AFS 11 min 18x
The results from the 2 simulators matched: code, supply current, comparator
outputs.
Circuit #2:
- 6 GB SerDes, simulated it in loop-back mode
- TIA; Limiting amp; Output driver; 40b Serializer & Deserializer;
Multiplying PLL; 6b ADC
- 21384 elements: bjt 4, mos 13024, capacitors 6706, inductors 2,
resistors 1616
Runtime
BDA AFS 29 hrs, 15 min
Spectre-* Did not converge
* - the other SPICE simulators he tried didn't converge either,
but he didn't name them.
AFS was able to simulate the entire SerDes, from power-on to CDR lock in
serial loopback. Further, they verified the accuracy by looking at the
signal going from PCB to the driver output. Since it was a schematic
simulation you wouldn't expect to see jitter, so AFS' 6.3 picosecond jitter
was the numerical noise, which was accurate for simulating large circuit
like a SerDes.
Circuit #3:
The speaker said they ran a PLL with 24 bit sigma delta modulator
which adds a lot of components to the circuit. Their approach is
to build Verilog models for sub-circuit, hook them together, and
then use AFS to simulate the entire PLL.
The PLL had 108,480 elements: MOS 18,150, extraction adds 90,300
capacitors to the simulation, so simulation times are prohibitive
in regular SPICE.
Runtime Speed-up
Spectre ~3 weeks 1x
BDA AFS ~30 hrs ~18x
The speed up means they are starting to use AFS as sign-off tool before
they deliver circuits to the customer. 3 weeks of simulation would usually
take them past their customers' tape-out time.
---- ---- ---- ---- ---- ---- ----
PLL lock accuracy: The speaker said they were excited to see that the
difference between AFS and actual silicon for lock time was just a fraction
of a nsec for both integer and fractional modes, as it shows AFS is
simulating critical voltages accurately.
AFS Silicon
Integer Mode
Lock time (ns) 15.6 15.8
Fractional Mode
Lock time (ns) 16.2 16.8
---- ---- ---- ---- ---- ---- ----
The speaker closed with a similar but smaller VCO transient benchmark that
had a 9X speed-up with AFS.
- [ Speedy Gonzales ]
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