( ESNUG 495 Item 5 ) -------------------------------------------- [11/11/11]
From: [ Speedy Gonzales ]
Subject: Berkeley AFS correlates to within 1% of final 40 nm CMOS silicon
Hi, John,
Here's what the last speaker at TechMart, Nandu Bhagwan of Analog Bits, said
about Berkeley AFS vs. final 40 nm CMOS production silicon.
Nandu said he built a PLL for 100 Gigabit Ethernet 802.3ba CDR applications.
The end product supports a 100G BASE-LR4/ER4 or 28G SERDES operation. The
CDR requires a very high-performance PLL, and his PLL had stringent jitter
specifications, which needed to be precisely analyzed and predicted.
He gave an example of block-level extraction for VCO operating at 14 GHz.
It was a schematic-based extraction, rather than an RC extraction.
Circuit Components
bsim4v5_0 280
bsource_c 257
bsource_i 187
capacitor 203
diode 2
inductor 180
mutual inductor 6
resistor 6
vsource 50
Runtime:
- BDA AFS simulation runtime was 23 minutes
- Using 4 Xeon X5460 quad core, running at 3.2 GHz
- Mostly this was for tstab, which was 400 ns.
After building his transfer functions Nandu calculated the total phase
loops. He said he saw a correlation of with %1 between AFS and silicon
across all frequencies.
silicon (dB) AFS + Eqn (dB)
-95 -95
-98 -97
-122 -123
-134 -136
Nandu concluded by saying that AFS was good for speed and accuracy, and
that the tool could use some improvement in the user interface. He said
his bottom line was that they taped-out based on AFS results.
- [ Speedy Gonzales ]
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