( ESNUG 495 Item 10 ) ------------------------------------------- [11/17/11]
From: Jeff Dyck <jdyck=user domain=solidodesign got calm>
Subject: How to run Solido with 100's of BDA licenses for custom design
Hi, John,
I saw some recent user pieces on Berkeley Design Automation AFS simulator.
Since we have customers using our Solido Variation Designer with BDA AFS and
we previously published these white papers on DeepChip:
Solido and Cadence ADE/Spectre/APS (primarily used for RF/Analog, I/O)
http://www.deepchip.com/look/see100608-01.html
Solido and Synopsys HSPICE/HSIM/CustomSim (for memory, std cell libs)
http://www.deepchip.com/look/see100730-02.html
I thought I'd add our "how to" for
Solido and Berkeley DA AFS (primarily for RF/analog, I/O, custom digital)
It's in 3 basic steps:
1. Using Solido with BDA by inputting a design through Cadence ADE.
2. Using Solido with BDA by inputting an HSPICE-compatible netlist.
3. Setting up Solido to run anywhere from a single BDA simulator to
100's of BDA simulators simultaneously on an LSF or Sun Grid Engine
(SGE) farm to design for PVT (process, voltage, temperature) corners,
statistical variation or high-sigma statistical variation.
CADENCE ADE USERS - STEPS FOR USING SOLIDO WITH BDA
1. Do schematic entry using Cadence Virtuoso Composer.
2. Set up ADE as usual to work with BDA. Use the "Switch to BDA" menu
option in ADE to automatically reconfigure your session to use the
BDA simulator.
a. Set up the analysis to run using ADE.
b. Set up the nominal model conditions in ADE.
c. Set up the typical environmental conditions as ADE design
variables.
d. Configure outputs within ADE.
e. For multiple testbenches, set those as separate ADE states and
save the states in the cell view.
3. Simulate at nominal using ADE and BDA. Ensure the netlist is
simulating properly at nominal.
4. Start Solido Variation Designer from ADE using the Solido->Variation
Designer menu option. Solido then opens an inter-process
communication channel with Virtuoso, and through a custom Skill
interface, Solido pulls all the information set up in ADE
automatically.
5. Solido automatically extracts from Cadence:
a. Default model sets; both global process corners and statistical
variables are automatically parsed out of the model files.
b. Environmental variables from the ADE design variables, as well
as their default settings.
c. Outputs as defined in ADE.
d. Design hierarchy and device parameters.
6. Solido automatically detects any changes in the design, so the view
in Solido stays in sync with Cadence.
7. Add additional testbenches by pointing Solido to the additional ADE
states that were created.
8. Specify any subcircuit as the device under test, allowing for
targeted variation analysis within higher-level designs.
HSPICE-COMPATIBLE NETLISTS - STEPS FOR USING SOLIDO WITH BDA
1. Create the netlist, either using a schematic editor and HSPICE
netlister, or by writing the HSPICE-compatible netlist by hand. Set
up testbenches using HSPICE syntax.
a. Set up typical environmental conditions using .temp and .param
statements for environmental conditions.
b. Set up measurements using .measure statements in the netlist.
Solido supports additional post-processing mechanisms, so if
what needs to be measured cannot be expressed in a .measure
statement, use Matlab, Octave, or other custom scripts for
defining outputs.
2. Ensure that the testbenches work correctly using BDA at nominal by
running in HSPICE compatibility mode from the command line.
3. Start Solido from the command line and create a project using any of
the netlists you created for your project. If using Cadence Composer
as the schematic editor, start Solido from the icfb main window to
make use of device selection and device highlighting within Composer.
4. Solido then automatically reads in:
a. Model files, including automatic extraction of global process
corners and statistical variables.
b. Environmental variables and default values from .temp and
.param statements.
c. Outputs from the .measure statements.
d. Design hierarchy and device parameters.
5. Solido polls the netlist file for changes, and automatically updates
the design properties in real time to account for changes to the
netlist.
6. Add additional testbenches by specifying more testbench netlists,
as long as the testbenches all contain a common subcircuit.
7. Solido, select BDA AFS as your HSPICE-compatible simulator.
STEPS TO SCALING SOLIDO WITH 100'S OF BDA SIMULATORS ON A COMPUTE FARM
In Solido, set up simulation jobs using local multi-core distribution,
Platform LSF, or Sun Grid Engine (SGE). Here are the steps:
1. Select the distribution mechanism from a Solido drop-down
box [local, LSF, SGE].
2. If LSF or SGE, pick the queue using a Solido GUI that
automatically queries all queues.
3. Specify the number of nodes to use.
4. Click OK.
Solido then manages the simulation job distribution highly efficiently.
Solido can be used to run 100's of nodes simultaneously, with far less
overhead than submitting simulation jobs individually.
Solido's parallelization approach reduces the per-simulation submission
overhead to near zero. We have seen this overhead at our customer
simulation farms range from seconds to hours, depending on how busy they
are.
Here is an example of the time impact for doing a 3-sigma Monte Carlo
analysis on a voltage-controlled oscillator (VCO) circuit, with 40
transistors.
BDA & Standard BDA & Solido 100 BDA & Solido
Monte Carlo Monte Carlo+ Monte Carlo+
28.3 hours 11.3 hours 7 minutes
Being able to reduce the submission overhead and smart sampling techniques
as shown above makes it feasible to do fast variation analysis during
design. From this point, you can run Solido's PVT+, Monte Carlo+ and
High-Sigma Monte Carlo+ packages using BDA as the simulator to analyze
variation effects, identify device sensitivities to variation and fix the
design. Results can be highlighted on a Cadence schematic to show device
sensitive hot spots.
- Jeff Dyck
Solido DA Saskatoon, Canada
Join
Index
|
|
