( ESNUG 497 Item 6 ) -------------------------------------------- [01/26/12]
Subject: Shawn barks that "Hey, Calypto does RTL power optimization, too!"
> We would like to have some user perspective on RTL-level power analysis
> and optimization. Specifically Apache PowerArtist/PowerArtistXP and
> Atrenta Spyglass Power. We are seriously considering using one in our
> next design.
>
> - [ Puss in Boots ]
> http://www.deepchip.com/items/0495-07.html
From: Shawn McCloud <smccloud=user domain=calypto not calm>
Hi John,
I noticed your reader [ Puss in Boots ] did not include Calypto PowerPro in
his list of RTL Power Analysis and Optimization tools to evaluate.
He should look at Calypto's tools. We have automatic RTL power opto via
PowerPro, as well as a manual/guided opto flow via PowerPro Adviser.
PowerPro does things that neither Atrenta nor Apache do - letting users
get a total power reduction of 10-30% across their SoC and up to 60% on
individual blocks.
1. Calypto Clock Gating:
- PowerPro uses formal methods and deep sequential analysis to enable
insertion of clock gates across register boundaries. We can
look across 100's of cycles, while Atrenta and Apache are limited
to only a few clock-cycles. This means Calypto finds many more
power reduction opportunities.
- PowerPro has a built-in RTL Synthesis Engine which includes global
optimization and datapath architecture selection. Our engine allows
PowerPro to correctly estimate the tradeoff between clock-gate
savings and power consumption using real vectors. When combined with
Calypto's deep sequential analysis technology, PowerPro is able to
prevent inserting gated-clocks which are never actually gated given
the representative input vectors. In this way, designers avoid a
situation where they gain nothing in power efficiency, and actually
increase power consumption due to the insertion of the extra logic.
2. Calypto Memory Gating
- PowerPro does low-power memory optimization, which includes unique
functionality to automatically insert memory gating control logic,
including light sleep. This eliminates redundant memory accesses and
reduces overall dynamic and leakage power. (Memory typically chews
up 70% of a chip's power.)
3. Calypto Equivalency Checking
- PowerPro is tightly integrated with our sequential logic equivalence
checker, SLEC, to formally prove any RTL changes haven't altered the
design functionality. Verification is usually the biggest time sink
in the design process, and SLEC eliminates the need for unpredictable
verification cycles following the power reduction process.
> 1. Did you get any significant power savings using it? How much?
> 2. What correlation to silicon results did you see?
> 3. What's the pricing/licensing model for it?
> 4. Ease of integration into a Synopsys/Cadence/Magma EDA flow?
[ Puss In Boots ] should revise his tool eval question list to:
1. What were your total power savings? Did you do the optimization
semi-manually or automatically, and how long did it take you to get
the power savings?
2. What accuracy metrics did you use to validate your power reduction
tool's low power design decisions?
3. What's the pricing/licensing model for this power-reduction flow?
4. Were your power savings maintained as you progressed through your
front-end and back-end flows?
5. How did you verify that any RTL changes did not impact functionality?
How long was this verification process?
I think you'll find Calypto does well in these areas.
Regardless, if there's only one take away that I want your readers to have
here is that Calypto does RTL power optimization, too! PowerPro looks
across 100's of cycles, while Atrenta Spyglass Power and Apache PowerArtist
are limited to only a few clock-cycles.
- Shawn McCloud
Calypto Design Systems Santa Clara, CA
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