( ESNUG 497 Item 7 ) -------------------------------------------- [01/26/12]
From: Trent McConaghy <trentmc=user domain=solidodesign not mom>
Subject: One Engineer's Trip Report of the recent CICC'11 conference
Hi John,
The Custom Integrated Circuits Conference (CICC) 2011 took place Sept 18-21
at the Doubletree Hotel in San Jose, California.
There were four paper threads, presented by speakers from industry and
academia. In addition, there were Sunday tutorials; a luncheon keynote;
and two end-of-day poster sessions with a few company exhibits, fueled by
appetizers and drinks.
Despite being a conference focusing on circuit architectures, I counted 29
papers with "variation," "mismatch," "calibration" or similar in their
title or abstract. This is a real issue.
Below are some interesting things I learned from the conference speakers,
related to variability, design challenges, device challenges, and EDA:
Mike Clinton (Sr. Member, Technical Staff, Texas Instruments)
- Double-patterning (DPT) is the big manufacturing challenge for <32 nm
nodes: TI is doing triple-patterning for <20 nm, for 50% area
savings. To get DPT compliance, TI found they needed litho designers
and standard-cell designers to co-design.
- Design challenges for <32 nm include: systematic & random
variability, power supply scaling (Vdd=0.5V at 15nm, argh), power
dissipation, and layout restrictions.
- EDA challenges for <32 nm: greater reliance on advanced statistical
methods (with transient simulation), accurate parasitic extraction,
explosion in design rules & restrictions, P&R scalability, big-chip
verification, proper DPT support in layout tools.
- At 28 nm, random / mismatch variation affects can increase logic
delay by 3x! Mismatch is no longer just a memory or analog problem.
PVT analysis that assumes a Gaussian distribution is too optimistic.
More advanced statistical characterization is needed. Random dopant
fluctuations (RDF) are the major issue; line edge roughness (LER)
and random telegraph noise (RTN) cause problems too for <=28 nm. TI
experiments found 4x less threshold voltage (Vth) variability for a
new tri-gate MUGFET, but its fin is a new source of variation.
- I/O pin counts are becoming saturated (3000 pins/die). Therefore,
TI does more serial communication, SoC -> SiP, and 3D via TSVs. TI
partitions horizontally by memory, microprocessor, and analog. They
are investigating variants of TSV manufacturing in FEOL, MEOL, vs.
BEOL.
Toshiro Hiramoto (Professor, University of Tokyo)
His team measured 1 million identically-sized transistors, manufactured on
a 65 nm process, and analyzed variability. Their findings were:
- Threshold voltage (Vth) could vary from 0.3V to 0.8V, which is much
wider than predicted by a Gaussian distribution.
- RDF was the major contributor to Vth variation, and size and oxide
thickness were not.
- RDF strongly influenced DIBL, COV, NBTI, and RTN effects too.
- SOI and intrinsic channel FETs are less susceptible to RDF.
At IEDM December 2011, he will present analysis over 1 billion transistor
samples (for high-sigma modeling)
M.K. Leong (TSMC)
- Discussed HP (high-performance) versus HPM (high-performance for
mobile) process technologies. HPM starts with HP, but addresses
challenges for low-power mobile apps, via mixed Vth, high-K, BTI
optimizations, and more. High-K metal gates have slightly improved
mismatch and flicker noise.
- Local variations, notably RDF and LER, are a big issue. In fact, the
smaller manufacturing windows mean there is less time to tune the
process to reduce effects of RDF and LER.
- Besides local variations, there are new "local to mid-range"
variations: proximity effects, stress, thermal effect, and more.
- "Need design guidelines to mitigate variations." TSMC has moved from
any-gate pitch to fixed-gate (40 nm) to single-gate pitch (28/22 nm),
along with many more guidelines on layout.
"Embedded Memory Trends" session
A. Kotabe (Renesas), Y. Tsukamoto (Renesas), Mohamed Abu-Rahma (Qualcomm),
and S. Chellappa (ASU)
Reminded us that memory designers have been dealing with variation a long
time, and it continues to be a pressing issue. Each speaker gave a talk on
how they designed or characterized their memory circuits under extreme
sensitivity to process variation.
James Meindl (Founding Director of Nanotechnology Research Center, and
Professor, Georgia Tech)
Gave a keynote on nanoelectronics, starting with its history and said we
can extrapolate from key nano milestones to predict the future.
1960-2010
- The 1981 invention of the scanning tunneling microscope (STM)
opened the door to nano experiments. Key milestones since were
the carbon sphere (buckyball) in 1985, carbon nanotubes (1990),
and graphene nanoribbons (2004).
- Feature sizes shrunk approx. 1000x (25 um to 25 nm);
- # transistors / chip grew >1e9x;
- # instructions/s (performance) grew > 1e6x;
- via improvements in instructions/cycle (more cores etc.) and
cycles/s (higher frequencies).
2010-2024 (Present/future)
- Scaling issues: gate tunneling current, device parameter
variability, subthreshold channel leakage, source / drain
resistance > channel resistance, and copper interconnect
resistance.
- Causes power & heat issues: in some modern chips, the volume of
the heat sink is 10,000x larger than the die.
- Possible device-level fixes include strain in channel, III-V
channel FETs, high-permittivity gate dielectrics, metal gates,
new FETs, lower-permittivity interconnect dielectrics, power +
clock gating, litho innovations, and EUV.
- Heat issues are even more painful in 3D; one new idea is
microfluidic cooling.
He said that graphene nanoelectronics has some advantages over
silicon (Si), such as 80x better carrier mobility than Si; but line
edge roughness (LER) is a big issue. Ultimately, scaling of
charge-based devices will be limited by thermal noise, in about
2020 (R.Heyes IBM). Options beyond charge-based devices include
"excitions" and "spin" / "pseudo-spin" devices, built via graphene
variants.
Trent McConaghy (Chief Scientific Officer, Solido Design Automation)
- I was invited to present on variation-aware flows and tools. I showed
an example of statistical design, enabled by accurate 3-sigma corners
and fast verification.
- I presented a new methodology for getting insight into statistical
variability during early-stage front end design (initial topology
selection and sizing).
- Interestingly, this approach (Fast Function Extraction or FFX) is
starting to be used in other applications such as circuit reliability,
analog test, and even web search (!)
Tajana Rosing (Director of System Energy Efficiency Lab, and Associate
Professor, UCSD)
- Discussed energy management, from handheld to data centers.
- Servers in Google data centers only have 30% utilization, in order to
meet 50-100 ms response time. But at 30% they still use almost all
the power.
- Her group reduced energy consumption by 40-70% via dynamic power
management at hardware and software levels, with the help of machine
learning. She expects that she could proactively manage thermal
issues too with similar techniques.
Jae-Sun Seo, then Paul Merolla (IBM Research)
- These two speakers gave back-to-back talks on "neuromorphic" chips
being researched at IBM, backed by DARPA.
- The chips are massive sets of "neurons" (computing elements that
output a pulse each time enough inputs go high), arranged in a
rectangular array of "synapses" (connections). Unlike some
neuromorphic approaches, they are all-digital to make process
migration easy. The digital neurons are much simpler than the
ARM-core "neurons" in the Spinnaker project.
- Target applications include better performance for traditional
machine-learning applications like speech recognition, and "a desktop
supercomputer for neuroscientists."
David Kaiser (Professor, MIT)
Gave a lunchtime keynote entitled "How Hippies Saved Physics." He
described how Bell's theorem of quantum entanglement, with its implications
of instantaneous communication, found a following among hippies, psychics,
and even the CIA before it was finally acknowledged by mainstream physics.
- Trent McConaghy
Solido Design Automation Saskatoon, Canada
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