( ESNUG 498 Item 3 ) -------------------------------------------- [02/07/12]
From: John Cooley <jcooley=user domain=zeroskew not calm>
Subject: Clueless TSMC Exec invokes 40 nm fiasco to explain 28 nm yields!
The drama started when at the IFS2012 conference in London, Future Horizons
CTO Mike Bryant said that "six out of ten of TSMC's 28 nm customers were
reporting yield problems." This was reported by ElectronicsWeekly.com,
EEtimes.com, and other web sources.
"Bryant said that there are 10 designs in manufacture from 7 companies.
"We're now hearing none of them work; no yield anyway," he told an
audience at the one-day market forecast conference. "Ten designs going
through; we have heard about problems on 6 of them," Bryant added.
- CTO Mike Bryant from EEtimes.com (01/20/12)
"Foundries have come under pressure to release cell libraries too
early -- which end up with designs that don't work," Bryant said.
In an effort to try and be seen to treat every customer equally,
TSMC is attempting to launch ten 28 nm designs from seven companies,
but it's not working out too well: "At 45-nm, only NVIDIA was
affected. At 28-nm any problems for TSMC will be problems for
many customers" said Bryant.
- from TechPowerUp.com (01/22/12)
Then 6 days later in EEtimes.com follows up with:
"Maria Marced, president of TSMC Europe, repeated what has been said
before by herself and other TSMC executives; that defect density
reduction is on track for the 28-nm node and ahead of where TSMC was
with 40/45 nm process technology at an equivalent stage in its
roll out."
- from EEtimes.com (01/26/12)
In other words that TSMC Euro bigwig had effectively said: "Hey, our 28 nm
is just as good as our 40 nm was, folks!"
WTF?
Any chip designer who had lived through TSMC 40 nm will tell you that it
was a two year yield nightmare that even got TSMC CEO Rick Tsai fired!
 
So that TSMC Euro bigwig might as well have said to us: "Well at least the
Costa Concordia sank slower than the Titanic did, folks!"
---- ---- ---- ---- ---- ---- ----
Here's an engineeer's letter back from the TSMC 40 nm days:
> 1.) What are your 2 or 3 biggest burning EDA/design/business/tech
> issues that you're facing over the next 3 months? (The more
> details you can give, the better.)
From: [ Inquiring Minds ]
Hi, John,
Please keep my name and company anon on this.
Our project is almost ready for tapeout but our VP is afraid of committing
to TSMC 40 nm because of their off-and-on again yield issues. To wit:
07/06/08 -- Rumors of first parts at 40 nm scheduled for late 2008,
then delayed to Jan 2009, then delayed to March 2009.
02/09/09 -- Charlie Demerjian reports TSMC 40 nm has leakage problems
and power saving at 40 nm will be "minimal to negative".
04/30/09 -- TSMC CEO Rick Tsai admits in a conference call to
analysts that "There have been difficulties with the
yields. 40 nm is a difficult technology to manufacture.
We understand the root of the problem."
06/11/09 -- Morris Chang takes back the TSMC CEO job from Rick Tsai.
06/12/09 -- Goldman Sachs downgrades TSMC from "buy" to "neutral".
07/01/09 -- FBR Capital Markets reports for 40 nm "we believe yields
are as low as 20 percent to 30 percent, which may explain
the recent management change."
07/31/09 -- DigiTimes reports "In response to TSMC's 40 nm yield issues,
Chang said rates have improved from 30% to 60%" at a July
investors conference. (i.e. the yield problem is fixed.)
10/07/09 -- UBS downgrades TSMC from "buy" to "neutral".
10/30/09 -- DigitTimes reports "TSMC said it has seen yield rates for
its 40 nm node drop to 40% due to chamber matching issues."
(i.e. the yield problem is back!) And "CEO Morris Chang
pledged the issue will be solved within the quarter."
11/10/09 -- Nvidia confirms in the conference call that they were supply
constrained due to TSMC low yield issues.
01/13/10 -- DigitTimes reports "TSMC has been struggling to increase
yields on 40 nm to over 70%, according to industry sources"
and Xilinx was moving to UMC to minimize risks.
01/20/10 -- DigiTimes reports that Mark Liu, senior VP at TSMC had stated
"that the chamber matching problems that had impacted yield
rates for the company's 40 nm node have been resolved" and
that 40 nm yield is "about the same level as its 65 nm node."
We don't know if we should double order TSMC and pray this is mostly true or
to focus our efforts on making UMC or Global as our primary. Suggestions?
- [ Inquiring Minds ]
http://www.deepchip.com/items/0484-05.html
---- ---- ---- ---- ---- ---- ----
So to reiterate what we saw in EEtimes.com last week:
"Maria Marced, president of TSMC Europe, repeated what has been said
before by herself and other TSMC executives; that defect density
reduction is on track for the 28 nm node and ahead of where TSMC was
with 40/45 nm process technology at an equivalent stage in its
roll out."
- from EEtimes.com (01/26/12)
WTF???? Does this TSMC Euro bigwig even have a clue about the utter fiasco
that the disasterous TSMC 40 nm roll out was???
- John Cooley
DeepChip.com Holliston, MA
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