( ESNUG 498 Item 4 ) -------------------------------------------- [02/07/12]

From: Shawn McCloud <smccloud=user domain=calypto not calm>
Subject: A wordwide survey of 744 engineers on RTL Power Optimization

Hi, John,

Calypto just completed its first annual blind worldwide survey on RTL Power
Optimization.  A total of 744 engineers and engineering managers responded.

Unless otherwise indicated, the percentages below are based on all 744
respondents.

TOP METHODS USED TO REDUCE POWER

   Question #1:

            "Please select the top two things you or your
             design group does to reduce power."

      Clock gating                        : ####################### 68%
      Power gating                        : ############ 35%
      Dynamic Voltage & Freq Scaling      : ########## 29%
      Multi Vth                           : ######## 24%
      Resource sharing                    : ######## 23%
      Memory gating                       : ##### 16%
      Data gating                         : #### 11%
      Do not know                         : ## 6%
      Other                               : # 3%

When we look closely at this data, we see that over 2/3rds (68%) of the
engineers utilize clock gating for power reduction; this makes sense
because clock gating conserves significant power with minimum cost in terms
of power consumption or area.  However, thoroughly investigating structural
and sequential opportunities across register boundaries to achieve
efficient clock gating can be an inordinate time sink.

The second most commonly used power reduction method is power gating (35%),
followed by dynamic voltage and frequency scaling (29%), both of which are
explicitly specified as a design decision through power intent
specification in form of UPF/CPF constraint file.

AVERAGE TIME SPENT TRYING TO MEET POWER SPECIFICATIONS

   Question 2: 

          "What percent of your time do you spend trying
           to meet power specifications?"

              0%            : ######## 8%
              5%            : ######## 8%
             10%            : ################## 18%
             20%            : ################### 19%
             30%            : ################### 19%
             40%            : ######## 8%
             50%            : ###### 6%
             60%            : #### 4%
             70%            : ## 2%
             80%            : # 1%
            >90%            : ## 2%
      Don't know            : ##### 5%

On average, engineers spend over a quarter of their time, or 26%, trying to
meet power specifications!  This number is based on the feedback from the
95% of respondents (707 engineers) who knew their approximate time spent,
including those engineers that were not even involved with power.  It
demonstrates how important and time consuming power reduction has become
in the design process.

TOP SELECTION CRITERIA FOR RTL POWER OPTIMIZATION TOOLS

   Question #3:

           "What are your top *2* criteria for selecting
            an RTL Power Optimization tool?"

      Maximum power reduction with
         minimum timing & area impact    : ################ 47%
      Accuracy of RTL power analysis     : ############### 46%
      Ability to easily verify RTL
         functionality is unchanged      : ########### 33%
      Automatic clock gating insertion   : ########## 30%
      Designer control                   : ######## 18%
      Hierarchical design support        : ##### 15%
      Automatic memory gating &
         light sleep support             : ### 9%
      Capacity                           : ## 5%
      Other                              : # 3%

As you can see, there was a virtual tie between "maximum power reduction
with minimum timing and area impact" (47%), and the "accuracy of the RTL
power analysis" (46%).  These two items go hand-in-hand.  It is vital
that RTL power estimation and optimization be done without going outside to
another tool and/or waiting for gate level information, as doing so adds
cumbersome and lengthy cycles and makes tradeoff analysis virtually
impossible.

The next significant item cited was the ability to easily verify that the
RTL functionality is unchanged (33%).  Project timelines are already
constrained, with verification dominating project time.  Design groups must
be able to readily confirm that no errors have been introduced as part of
the power optimization process, as such errors would introduce unacceptable
risk to meeting project deadlines.

Only 9% of the engineers surveyed cited "Automatic memory gating and light
sleep support."  At first look, this seems low given that memory can
account for 70% of a design's power consumption.  However, a lot of
features, such as light sleep, are only available for 45 nm processes or
lower.  As designs move to 45 nm and lower, this memory gating and light
sleep support will become more important.

WHY I'M HAPPY

Using automation to optimize for power reduction early in the design
process, during RTL, can yield far more power savings than manual methods
and in less time.  I'm happy to say that Calypto PowerPro has got this
nailed.  It has an RTL synthesis engine under the hood to estimate your
hardware architecture (within the 15% range) so it can do correct design
tradeoffs 'real-time' during the power optimization process.  It also uses
deep sequential analysis to automatically implement power reduction at a
level that is almost impossible to do by hand.  Finally, PowerPro is tied
closely to Calypto's SLEC formal verification to immediately ensure that
the optimized RTL is correct.

    - Shawn McCloud
      Calypto Design                                    Santa Clara, CA