( ESNUG 499 Item 4 ) -------------------------------------------- [02/23/12]
Subject: Users voting to save Magma SiliconSmart
FIGHT FIRE WITH FIRE: In the library characterization space, Cadence bought
Altos to take on SiliconSmart. It seems fitting that SNPS picks up the
SiliconSmart side of this battle. Users like SiliconSmart throughput;
some liked that they could use it with their choice of simulators, others
preferred the SiliconSmart ACE + FineSim combo. The toughest hurdles it
passed were for complex memories.
"Assuming the Synopsys-Magma merger goes through, as a Magma user,
which specific Magma tools do you want to survive and why?"
---- ---- ---- ---- ---- ---- ----
We would really like to see Synopsys invest further advanced R&D work in
SiliconSmart Memory ACE in the future.
We previously had other 3rd party commercial EDA tools in house for a
long time, such as Synopsys NCX, Synopsys Library Compiler, and Cadence
Encounter Platform. None of the above can be compared with Magma
SiliconSmart's methodology. Not only does SiliconSmart come with the
full capability to help both circuit designers and digital library
designers cooperate together smoothly, but it also helps chip level
integration engineers to expedite debugging memory IP at SOC level.
The following capabilities of SiliconSmart have helped Atmel
enormously:
(1) Easy to embed with our in-house Sun Grid Engine (SGE) and LSF queue
mechanism, which relieves the burden from our IT engineers.
(2) High performance circuit pruning features, which can dramatically
reduce characterization simulation time dealing with large memory
characterization.
(3) User friendly editable memory template mechanism, under such
circumstance, memory designers no longer need to hand build functional
table from scratch in the instance file.
(4) By utilizing Sun Grid Engine (SGE), LSF queue mechanism, and circuit
netlist pruning function, our memory characterization simulation time
can be cut in half. (Several days decreased to 1~2 days).
We have used Magma's SiliconSmart on following process technology
nodes, 0.18um, 0.15um, 0.13um, 90nm, and 65nm. We also have various
commercial memory compilers in house.
Magma SiliconSmart Memory ACE can fully function with all of the above,
and fully implement memory characterizations on 100+ instances, some of
them are with large density such as 256KB. Furthermore, the final
generated memory liberty files can be formed in various industry
standard liberty formats, such as NLDM, CCS, ECSM, CCS Noise, etc.
Finally, Atmel also has FineSim in house as standard sign-off simulator.
When SiliconSmart is combined with FineSim, final generated liberty
files will have the optimized timing. It is extremely important for us
when chip level integration engineers trying to optimize chip
performance at SOC level. Magma SiliconSmart and FineSim are a key
part of our delivering optimized re-characterized memory liberty files.
I have listed some runtimes below.
SiliconSmart + FineSim Runtimes
w/o SS pruning With SS pruning
Uses Sun Grid Engine No Sun Grid Engine
Memory name Performance Performance
(minutes/corner) (minutes/corner)
hsspsramlvt_2048x72 3600 480
hsspsram_2048x72 3600 480
hsspsramlvt_2048x32 1600 150
hsspsram_2048x32 1600 150
The two sets of data above used the same server and the same amount of
physical memory. These 2 memory instances are very important in our
ARM SOC.
- Church Chiu of Atmel
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We replaced our internal cell characterization tool with SiliconSmart
several months ago. It is a useful circuit characterization tool,
especially with complex I/O pads.
Since we preferred to use our own circuit simulator, the Magma team was
able to integrate it into SiliconSmart. The set up process was easier
than our internal characterization tool, and the control files were much
smaller since we don't have to hard code every stimulus waveforms.
SiliconSmart creates stimulus waveforms by analyzing our logic
description of the cell. And we have full control of how each timing
arc was characterized. The total runtime is about the same between
SiliconSmart and our internal cell characterization tool, but this is
because we are using the same simulator.
SiliconSmart also lets us add extra elements to the characterization
setup, such as attaching analog bias circuitry as part of the
characterization environment. This creates much better models because
the bias circuitry tracked the PVT conditions along with the pad we were
characterizing. Just like any other tool, there will be a learning
curve, but SiliconSmart proved to be a useful tool, once we mastered
its capability.
Bottom line is we do want to keep SiliconSmart when the acquisition
occurs.
- Trong Nguyen of Freescale
---- ---- ---- ---- ---- ---- ----
APM has been using Magma SiliconSmart ACE for characterization for a
couple of years now and have delivered several versions of .lib files
using this product.
Our characterization requirements are very complex and our
flows/methodologies are highly customized to meet the high speed and low
power requirements for our .libs.
SiliconSmart's ability to easily adapt to these flows is one of its
most significant advantages for us. It is also one of the primary
reasons, why we switched from a competing solution. Other key technical
advantages include:
- Integrated platform to characterize a broad range of IP's such as
Standard Cells, Custom Digital Cells, I/O's like GPIO, LVDS & DDR, and
Memories.
- The excellent AE support and R&D responsiveness from Magma are the
icing on the cake that has made us very successful in using this
product.
- Capacity advantages to characterize fully extracted memories. All the
examples below were run with 25 CPUs.
SiliconSmart
Memory throughput
--------------------- ---------------
128x160 SP SRAM 17 hours
32x64 2P RAM 3.5 hours
1024x137 SP SRAM (~1M transistors) 23.5 hours
SiliconSmart had throughput to characterize fully extracted memories
within practical runtimes, which was not achievable with our prior
solution.
- Kenny Tung of Applied Micro
---- ---- ---- ---- ---- ---- ----
We would definitely want continued support for Magma's Library
Characterization tool SiliconSmart. We had been using a tool for
almost 3 years for standard cell characterization, but we had no memory
characterization tool before we started evaluating SiliconSmart.
We chose SiliconSmart for characterization of our standard cell
libraries as well as for our custom memory characterization. Our
primary reasons were:
1) Liberty characterizations are within 5% of accuracy when correlated
to SPICE/SPECTRE simulations.
2) A typical standard cell library consists of 126 cells that can be
characterized in a 1.5 hour timeframe.
3) Ability to efficiently re-characterize a Vendor .lib at a new PVT
corner or build a standard cell .lib from scratch using the tool's
functional recognition feature.
4) Ability to use embedded or standalone FineSim as the simulator.
5) Ease of use model, and the setup files are easily portable in new
designs.
6) We have ROM and SRAM kind of memories that can be characterized using
SiliconSmart, and like that the tool can automatically detect the
internal 'bit cell' node of the memory for constraint (setup/hold)
measurements.
7) SiliconSmart ACE for memory characterization has a number of
optimization features such as acceleration of setup/hold
measurements, smart netlist pruning using which gave us very good
throughput.
Memory Throughput
----------- -----------
4KB size SRAM 5 hours
8KB size ROM 5 hours
There are other features of the tool that are very useful such as
Verilog model generation and SDF back-annotation, and Datasheet
generation.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I am writing in hopes that Synopsys will continue SiliconSmart.
I have used (and worked with other engineers that have used) our
internal company characterization tool. The engineers agree that our
internal tool is difficult to use and not well documented. To be more
specific, defining the input constraints (slews, loads, etc.) and
defining the desired timing arcs was not intuitive and debugging was
very difficult.
Although SiliconSmart took me some time to understand how things work,
the documentation is good (not great) and I got the job done. In my
case I spent several weeks (on and off) trying to get a working liberty
file. Some of time spent was attributed to not knowing the circuit,
while most of the time was spent trying to understand how to get enough
information out of the tool to debug issues. Once that was done things
seem to run smoother which is the case for almost any tool.
I did not compare SiliconSmart's results to our internal company tool
but I did compare the timing results to what the designers were
simulating so I feel comfortable that the timing is correct.
I characterized two libraries which included three scribe IO cells and
two digital IO cells which were a bit more complicated. The digital IO
cells included some setup and hold requirements for internal latches.
I was not able to get Spectre or FineSim results and had to resort to
using Eldo. Due to time constraints I was not able to get these issues
resolved with the support engineer.
I can say that the tool pointed out some issues with the circuits that
were being characterized. In essence, SiliconSmart appears to be a
tool that could and should be used to validate functionality and corner
related issues for timing.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
We have gone through a generation of tools in the past 10 years to
satisfy our characterization needs. We evaluated Magma SiliconSmart
4 years ago and have had a very good experience with it in terms of
throughput as well as accuracy.
Apart from a few custom designed cells, most of our standard cell
libraries come from vendors. For this purpose, the re-characterization
flow supported by SiliconSmart is our most used feature.
1. It is easy to setup and use
2. Pretty much automatic, quicker turnaround time for characterizing
multiple PVTs
3. Eliminates effort to re-define cell functionality, load/slope
conditions, attributes, etc.
4. Easy to add CCS noise constructs to existing Liberty models
We switched from our in-house semi-automatic characterization solution
to SiliconSmart when we saw almost a 5x runtime improvement for
standard cells and good accuracy correlation with our internal SPICE
engine.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I would definitely want to see Magma's SiliconSmart characterization
tool survive.
My company uses a custom process and we must design our own standard
cell libraries. I previously used Nangate Creator and Characterizer,
combined with HSPICE LSF farms (not NanSpice) to develop and
characterize our library. The tool worked well for cells that I
developed using their front end tool. However it was very difficult to
use the characterizer tool to characterize other cells which were not
developed by the tool.
I evaluated SiliconSmart for characterizing our standard cell libraries
and complex I/O cells. After benchmarking it against our previous
characterization tool, I decided to adopt SiliconSmart for deployment.
Some of my key reasons:
1. For both tools, characterized values for timing and power are within
5% of spice accuracy. With SiliconSmart, I also see better run times;
approximately 1.5X faster with SiliconSmart as compared to our previous
tool. The use of Magma's FineSim embedded simulator allows me to not
have to compete for simulation licenses with the other designers.
Using the 5 embedded FineSim licenses, I can characterize my library of
945 cells with full ccs timing, power, and noise overnight. I have not
tried using SiliconSmart ACE with HSPICE since this is always a
competition with the rest of the company for licenses, so it is not an
apples to apples comparison. I don't know how much of speed up is due
to ACE verses simulation engine and license checkout time.
2. Characterizing complex I/O's was time consuming with our previous
tool since it involved post-processing & scripting to finalize the
timing and power models. For example, I had to characterize the I2C
control circuit as two individual runs: once for the standard mode
operation and then again for the low speed mode operation. The models
had to be finalized after manual post-processing and merging the
timing/power data from the two separate runs.
With SiliconSmart, I was able to set up characterization for the I2C
control circuit for both operating modes in the same run and no
post-processing was required. SiliconSmart allows much more
flexibility in specifying the way a cell it to be characterized and what
arcs to consider.
3. I have I/O cells with many configurable options pins which do not
affect the functionality of the cell but do impact timing/power. In
SiliconSmart, the setup for these cells is straight forward; I was
able to tie the pins to a fixed voltage and go through with
characterization and modeling.
4. Even complex I/O cells like differential and bi-directional I/O cells
are very easy to setup. Once you have a template, additional
characterizations are very simple.
5. SiliconSmart also has a re-characterization feature that allows me
to very quickly read in a previous PVT corner, change to a new PVT and
run characterization with the exact same timing arcs, when conditions,
etc.
6. During characterization, I often run into failing simulations and
need to debug. SiliconSmart specifies which simulations failed for a
specific cell in the log file and also, depending on the type of issue,
gives suggestions about the parameter to customize which would help
resolve the issue. The failed simulations are left unzipped in the
spice run directory. All the passing simulations are tarred and zipped.
So, when navigating the spice run directory it is easy to identify the
failing deck and re-simulate, if needed for debug purposes.
Also, SiliconSmart natively has validation features which alert you to
questionable values in the models in the Liberty file.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Magma SiliconSmart is a tool that Synopsys should choose to carry
forward.
SiliconSmart is the most complete library characterization solution
that I have evaluated, and is now a part of our custom design flow.
Our group creates custom datapath IP blocks, and other logic elements
for a high speed fabric; turnaround time and accuracy are crucial. I
was searching for a tool to complete a flow linking our custom designs
into an ASIC environment for verification, timing, and power analysis.
SiliconSmart was the most complete solution available for modeling the
essential complex base blocks.
I have been a user of the tool for 3 months now. The learning curve was
very small and there were some hiccups but the tool provided enough
diversity to meet my end goals.
SiliconSmart's ability to model complex circuits is a plus but I prefer
to model the cells myself and the tool has a very simple and intuitive
flow for this task. I can quickly model and verify my circuits by
describing the actual behavioral code from my golden behavioral logic in
their Verilog/Liberty like language, then let the tool time out my paths
and verify my SPICE circuit correctness to the logic. The debugging
ability of the fail runs can be a little difficult because of messages
that don't really indicate the problem, but you quickly learn what to
look for.
I use SiliconSmart's embedded FineSim, external FineSim, and ELDO
simulators seamlessly for my SPICE simulations. The embedded approach
is very fast because the tools takes advantage of embedding and models
more efficiently than using external solutions. Unfortunately I can't
quantify this point as yet as I am currently still in the process of
evaluating the accuracy of the SPICE data and correlation between these
3 simulators.
I have used this flow on 65 nm down to 28 nm designs.
- Devon Matthews of Stretch, Inc.
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