( ESNUG 501 Item 5 ) -------------------------------------------- [04/04/12]
Subject: A second user eval of Calypto PowerPro-CG and PowerPro-MG tools
> It took me around 2 days to set up the Calypto tools, with remote support
> of a Calypto AE. For a second design, I expect set up to only take 1 day.
>
> Before Calypto After Calypto Change
> --------------- -------------- ---------
> Power 32 (mA) 29 (mA) - 9.4%
> Area 6.4 M sq mm 6.45 M sq mm + 0.8%
> Gated flops 65% 75% + 15%
> Timing clean passed timing N/A
>
> Our test case was an existing 3 M gate design that we had already hand
> tuned for power. In 5 hours we got another 9.4% power reduction from
> the Calypto run!
>
> - from http://www.deepchip.com/items/0500-05.html
From: [ Chicken Little ]
Hi, John,
Anonymous please.
Here's my recent eval of Calypto PowerPro tool for RTL power optimization.
It has two power optimization approaches available:
1. A guided optimization flow (which lets you manually
control your optimization decision)
OR
2. An automated power optimization.
We evaluated Calypto's automated power optimization and not their guided
flow, because we felt an automated optimization had a higher potential for
saving engineering time and improving productivity (i.e. it's not really
useful if it takes a lot of hand holding.)
Calypto has two flavors of automated power reduction:
1. Clock Gating (PowerPro CG) - we evaluated this tool ourselves.
2. Memory Gating (PowerPro MG) - evaled in taxi-cab mode, where Calypto
ran the tool onsite at our facility.
We tested PowerPro on design blocks up to 2 M gates, with clock speeds
~1 Ghz. The process node was TSMC 40 nm. For both the clock-gating and
memory-gating evals, the block sizes went up to ~2 M gates. We designed
the blocks in Verilog and System Verilog.
POWERPRO-CG (CLOCK GATING)
Calypto clock gating involves creating new enabling conditions for the
sequential elements in your design. It gates the sequential elements,
and also extends the time the data paths are gated between sequential
elements -- as compared with regular clock gating.
Calypto averaged a logic clock gating efficiency of about 15-20%, which
resulted in ~10% power reduction to the block.
Here's a representative example below.
EXAMPLE: 500 K gate block
After Power Compiler
Before PowerPro After PowerPro Improvement
----------------- -------------- -----------
Clock Gating
Efficiency 50% 65% 15%
Power
Consumption 200 mW 180 mW 10%
Note: we did not spent any human engineering time optimizing our design
for power, other than running it through Synopsys Power Compiler. After
Calypto's optimize RTL run, we used Synopsys PrimeTime-PX to measure the
power consumption through Design Compiler and Power Compiler to get to
the gate level.
The runtime was about 2-3 Hrs.
We also ran a test case to assess Calypto's runtime for a large block:
EXAMPLE: 2 million gate block
Calypto PowerPro Runtime: 6 hours
The runtime depends more on logic structure rather than the number of gates.
POWERPRO-MG (MEMORY GATING)
For memory gating optimization, you can think of the memory as basically a
flop - except a lot more complicated, since it both stores data and has an
address and enabling condition. So in one way, memory gating is like clock
gating in that you are doing sequential analysis for flop stages and adding
enables.
Calypto PowerPro checks what the memory gating conditions are. For example
if the memory data was not observed in the second stage, then it is more
efficient not to read the memory in the first stage. Calypto knows how to
quantify the READ and WRITE operations. They characterize it by building a
PowerPro memory model in their own format, and they read the model in to do
their analysis and memory gating optimization.
As our memory power is significant, PowerPro MG was worth checking out.
I don't have one representative design comparison for this, but the average
improvement over the sample of designs tested was in the 5-10% range on
memories running at 750 M hz. (Keep in mind this data is from an onsite
taxi cab mode eval -- we did NOT run PowerPro MG ourselves on this part!)
PROBLEM: There was an issue where we had to blackbox a sub-module in a block
because PowerPro-MG was running out of memory. But Calypto already fixed
this in a later version.
CALLYPTO SLEC & CADENCE CONFORMAL:
Calypto has their SLEC RTL equivalency checker in integrated with PowerPro.
Their AE did the SLEC runs for both our PowerPro-CG and PowerPro-MG evals.
I did the Cadence Conformal runs myself.
Since the power reduction logic Calypto adds is an "enabling" condition,
Calypto gives you a global override to turn off all "enables" to do formal
verification with Cadence Conformal LEC. I used the override to turn off
all the enables, and then ran the optimized RTL through Cadence Conformal.
It compared.
Of course turning off the "enables" before silicon would nullify the power
savings, but it was still a good check until I can test it in silicon. I
will continue to use Conformal LEC following PowerPro/SLEC until I have
real silicon to prove SLEC's results.
CONCLUSION:
We like that we always have the option to turn "on" PowerPro's optimization
after silicon, or override the Calypto optimization (turn off "enables")
if we find any issues. If something's wrong, no respin needed!
Our designers spend about 30% of their time on hand power optimization
(~1.5 days out of 5 days), so we see some potential for Calypto's auto-flow
to save engineering time.
However, we have not yet formally compared the time spent using Calypto's
auto-flow versus doing it manually, as we would need to assess not just
power optimization time, but also timing analysis, verification, and ECO.
SLEC should help, but we still need to do more testing there to get
comfortable with it.
Based on the un-optimized designs that we tested, I would expect ~10% power
reduction from PowerPro CG and a 5-10% power reduction from PowerPro MG.
Not bad numbers for two simple tool runs.
- [ Chicken Little ]
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