( ESNUG 502 Item 3 ) -------------------------------------------- [04/19/12]
Subject: Cadence says it's strong in Specman "e" yet language neutral
> From their actions and inactions, it's obvious Cadence Marketing decided
> some time ago that they see Specman "e" as a dying product to be milked
> for as much $$$ for as long as possible while they focus their energy
> on the fight with Synopsys and Mentor over System Verilog market share.
>
> - from http://www.deepchip.com/items/0501-02.html
From: Kishore Karnane <karnane=user domain=cadence not calm>
Hi, John,
Contrary to these two recent posts, Cadence has been promoting Specman "e"
quite aggressively the last two years. I know you won't take my word for
this because you don't trust EDA marketing people, so here's my proof.
Specman "e" Customer Endorsements 2010-2012
- PMC Michael Blech e vs SystemVerilog Comparison -
- Vera dying, but Specman "e" is quite alive and well! -
- ST Microelectronics Geoffrey Faurie Blog Interview -
- Siemens Thomas Kraus Success Story -
- Fujitsu Raimund Soenning verifying many configuration IP -
- Ericsson Dahir on Specman Constrained Random Verification -
- Why the e Verification language is Alive and Well at Cadence -
- LSI Mixed Signal Success Story -
- Specman e Users on Benefits of e over System Verilog -
- Cadence Boosts Verification Productivity for FPGA/ASIC Design -
- My Reason For Choosing e, What's Your Reason? -
Specman "e" Webinars 2010-2012
- Look Smarter with Incisive Debug Messages Analysis -
- Apples vs. Apples HVL: Choosing a Verification Language -
- Apples or PC's? e or System Verilog? -
- Incisive Debug Message Analysis Webinar -
- Improve verification by 40% with Specman Advanced -
- Specman e Source Debug with SimVision -
- Losing Sleep on Mixed-Signal SoC Verification? -
- Learn Aspect-Oriented Programming-Verification -
Specman "e" DVcon 2010-2012 Papers
- Apples vs. Apples HVL Comparison Finally Arrives -
- Mixed Signal Verification of Dynamic Adaptive Power -
- Where OOP Falls Short of Hardware Verification Needs -
- Medical Metric Driven Mixed-Signal Verification -
- Mixed-Signal UVM-MS Metric Driven Verification -
- Mixed-Signal UVM-MS Metric Driven Verification -
- HW/SW Co-Verif with Specman, SystemC, and TLM Ports -
- UVM-MS brings MDV to mixed-signal SoCs -
Specman "e" CDNlive 2010 Papers
- Automated Self-Checking M/S Verification using Specman-AMS -
- OVM-E for Scalable Test Bench from IP to SOC level -
- Creating VIP for Network On Chip based protocol using 'e' -
- Constrained random and coverage driven verif of Embedded SW -
Specman "e" Ecosystem Partner Blogs
- Verification inter-operability beyond UVM -
- Rejuvenation of IEEE 1647-E language -
- Increased user momentum at CDNLive India -
- Welcome to Advanced Specman -
- DVT "e" Language User Guide -
- UVM beyond System Verilog to support "e" -
CDNS Team Specman Blog Posts 2010-2012
- Verification Productivity with Specman Advanced Option -
- e or System Verilog for Constrained-Random Verification? -
- If Only Carl Friedrich Gauss had IntelliGen in 1850 -
- Full Sequence Coverage in a Single Line of e Code? -
- Is e Old? Yes. Is it Outdated? Definitely Not! -
- Specman Application Note: Dynamic Load and Reseeding -
- Applying Digital-Centric Verification Methodologies to Analog -
- Support for e Language Macros in Amiq DVT Tool -
- Update on AMIQ's DVT IDE at DAC 2011 - Specman Debugger -
- Technical Tip on How to Use HDL Assertions in e -
- e Templates and e Macros -
- Users Employ Specman Constrained-Random Verification -
- Ericsson Selects Specman Constrained-Random Verification -
- Advanced Option Brings New Features to Specman/e Users -
- Performance Tips - Coding e Ports for Enhanced Performance -
- Performance Tips - Another Specman Performance Series -
- Specman e Templates: A Nifty Way to Create Reusable Code -
- Specman e Templates and Aspect Oriented Programming -
- Sign Up for Verification Sessions -- Only A Few Days Left -
- IntelliGen Moving Into The Spotlight With Pgen Deprecation -
- Specman, e, and EDA 360 -
- India Takes The Lead By Hosting The First Two "ClubTs" in 2010 -
- Informative Tweets on WHEN Inheritance -
- 2010 CDNLive Munich Guide for Specmaniacs -
- Verified by e/Specman: Palladium XP Computing Platform -
- Specman-SimVision webinar on April 22 -
- Is e Really Up to 3x More Compact Than System Verilog? -
- Is e Really Up to 3x More Compact Than System Verilog? (pt II) -
- Is e Really Up to 3x More Compact Than System Verilog? (pt III) -
- Free eVC Generator From CFS Vision Update -
- Built-in Message Logging - Part 1 of 2 -
- Built-in Message Logging - Part 2 of 2 -
- VIP Portfolio Extension: New AMBA 4 Protocol Support -
- Why OOP Falls Short For Verification -
- Rev 2 of OVM e Scoreboard on OVMWorld.org Now -
- Cadence Exec: Why Cadence is Committed to e Specman -
- DVCon 2010 For The Specmaniac -
- Adding Arbitrary Metrics To Your Metric-Driven flow -
- Tech Tip: Easy Way To Re-Run Using The Same Seed -
- Tech Tip: Waving Specman Objects in SimVision -
Here's some of my favorite quotes that I extracted:
"I noticed an approximate productivity drop of 30% when teams switch
from e to System Verilog."
- Geoffrey Faurie, ST Microelectronics
"Estimates that switching from "e" to System Verilog (assuming one is
a proficient user of "e") will cause a 30-40% productivity loss."
- Michael Blech, PMC-Sierra
"Why go for the second best solution (System Verilog), when we can go
for the best solution (Specman "e")?
- Raimund Soenning, Fujitsu Semiconductors Europe
"Comparing "e" and System Verilog is like comparing a screwdriver to
a knife. A knife was designed to cut food, but it can also be used
to drive screws with less efficiency."
- Geoffrey Faurie, ST Microelectronics
"Why not ask Synopsys for their e-solution? It's an open secret that
SNPS supports "e"."
- Darren Galpin, Infineon
"System Verilog is not just an extended version of Verilog. While the
naming was successful, it's actually a new object-oriented language.
More than two-thirds of the [System Verilog] language is actually
something new. Designers have to learn what object-oriented is all
about."
- Michael Blech, PMC-Sierra
"Vera is dying, but Specman "e" is quite alive and well!"
- John Cooley, DeepChip.com
Perhaps at times we promoted System Verilog at the expense of "e", but as
you know, we live in a multi-language world. As the only EDA company
*openly* supporting *all* industry standard languages including Specman "e",
System Verilog, SystemC, Verilog, VHDL, etc. we had to make some tradeoffs
in terms of promotions, but one message should be clear: We continue to
invest in Specman "e" and have made many next generation advancements in
our "e" solution.
Unlike Synopsys and Mentor, we understand that different customers prefer
different languages, which is why we are driving multi-language support for
UVM within Accellera -- so that we can let users decide which verification
language is best for them.
> My CAD department likes the idea of second sourcing for all SW we use. It
> would be a *big* help if we knew of any good quality non-CDNS Specman "e"
> simulators. (Neither SNPS/MENT will tell of these because they're too
> invested in having us switch everything over to System Verilog.)
>
> - from http://www.deepchip.com/items/0495-02.html
Since it's no secret SNPS and MENT support "e", I agree that it would be
great if they'd finally publically open up about their competing "e"
technologies so users can get the right info to choose the best solution.
Cadence is committed to providing the best solution for *each* language in
a *single* simulator (Incisive) and methodology (UVM) -- period.
- Kishore Karnane
Cadence Design Systems, Inc. San Jose, CA
---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ----
> However Cadence made several strategic mistakes in this game & downplayed
> Specman "e" while making strong statements about supporting the System
> Verilog IEEE 1800 standard. While there were customers and vendors who
> were willing to be more bullish in supporting "e", it seems like Cadence
> was sheepish and focused on marketing its System Verilog support and not
> pushing the multi-language support as something which was needed.
>
> - from http://www.deepchip.com/items/0500-03.html
From: Mike Stellfox <stellfox=user domain=cadence not calm com>
Hi, John,
Since I worked at Verisity starting in 1998 as an AE and later lead the
Verisity Technical Field Organization until we became part of Cadence in
2005, where I am still working, I would like to offer my view of this.
As the Mouse describes very well, the story of "e" vs. System Verilog is
very similar to what already happened with Verilog and VHDL. In many
ways, "e" is similar to Verilog in that it was developed by a single
company and became a defacto standard before it became an IEEE standard.
Anyone who has worked with both "e" and System Verilog can tell you how
"e" is a simpler, more powerful, and streamlined language for verification
where on average it requires roughly 1/2 the lines of code compared to
System Verilog, i.e. just read what customers have recently posted on
ESNUG 488-05:
"The other thing to consider is that the code base for a System
Verilog testbench will be at least 30% or so bigger for the same
type of testbench that you would do in "e" -- and as the number
of testbench bugs correlates to the number of lines of code you
have, you'll have 30% more testbench bugs to fix as well."
- Darren Galpin of Infineon
Similar to the history of Verilog where many customers preferred to stay
with Verilog, many "e" customers see no compelling reason to move to
System Verilog and usually see it as a step backwards.
In contrast to what some EDA Marketeers would have you believe, there are
many "e" customers today and the user base continues to grow. I personally
have worked with several companies who tried switching to System Verilog
and found the productivity LOSS to be too great so they ended up staying
with Specman "e".
At this point, I am sure there are some readers out there thinking, "oh,
this is just another 'e' diehard giving a one-sided view", so let me get
back to the history lesson.
After joining Cadence, my team started working with the Incisive System
Verilog team to help shore up the Cadence System Verilog solution. The
first thing we did was take the successful methodology we developed at
Verisity as the "e" Reuse Methodology (eRM) and applied it to System
Verilog, which eventually lead us to releasing the OVM with Mentor Graphics
back in 2008. (BTW, we built OVM to support multiple languages and
Cadence supports both OVM and UVM for both "e" and System Verilog -- since
it is the same methodology based on eRM -- as well as connecting to SystemC
models.) As everyone is aware, the OVM was very successful in the industry
which helped put Cadence in a strong System Verilog position, and led to
Accellera later choosing the CDNS OVM over SNPS VMM in 2009 to be the basis
of the standard now known as the UVM.
During all this time when the initial System Verilog simulators were coming
to market, Cadence R&D didn't stand still on the Specman "e" -- since many
of our big customers were using "e" and driving R&D to make significant
advances in the Specman technology, including the Intelligen Constraint
Solver and the Specman Advanced Option in recent years.
> This enabled Synopsys to push System Verilog even more and create a drift
> towards System Verilog. The Synopsys management is very smart, and they
> realized quickly that, no matter what, they will still have to support
> Specman "e" if they don't want to leave those customers to Cadence, and
> they did a good job doing it.
>
> - from http://www.deepchip.com/items/0500-03.html
Perhaps Cadence did not strike the right balance during this time but let me
give some insight into this since I was involved in the strategy. At the
time, since Cadence had acquired Verisity, which was doing well in HVL
Testbench Automation, our competitors did a great job of spreading FUD that
Cadence was not serious about System Verilog which is supposedly why we
promoted "e".
Many customers were interested in System Verilog since all 3 vendors were
promoting it and publically supporting it, and it was the "new thing".
Since Cadence was interested in providing the best verification solution for
*both* System Verilog and "e" customers, this put us at a disadvantage to
our competitors, in terms of perception with potential SV customers. So,
right or wrong, this was the main reason we conscientiously did more System
Verilog marketing over Specman "e" marketing for a few years.
Flash forward to the present.
Cadence now provides a leading System Verilog UVM solution (largely from
leveraging our long experience with "e") and we've made many next generation
advancements in our "e" solution in the mean time.
We understand different customers prefer different languages. Our goal is
to offer the best multi-language integrated solution on the market.
- Mike Stellfox, Cadence Fellow
Cadence Design Systems, Inc. Austin, Texas
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