Yunshan Zhu of NextOp on the DAC'12 Troublemaker's Panel

( ESNUG 507 Item 4 ) -------------------------------------------- [07/19/12]

Subject: Yunshan Zhu of NextOp on the DAC'12 Troublemaker's Panel

     

     Yunshan Zhu of NextOp discusses verification Assertion Synthesis,
     Jasper, Cadence IFV, Mentor 0-in, SNPS Magellan, checkers, vectors,
     driving Verilog sims, Joe Sawiki, Questa, MENT Verification Academy,
     RTL market is 100's of M of $$$, selling against Synopsys/Cadence
     package deals, "partnerships" with Synopsys and Cadence.

Join Index Next->Item

"Relax. This is a discussion. Anything said here is just one engineer's opinion. Email in your dissenting letter and it'll be published, too."
This Web Site Is Modified Every 2-3 Days
Copyright 1991-2024 John Cooley. All Rights Reserved.
| Contact John Cooley | Webmaster | Legal | Feedback Form |


   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)