( ESNUG 518 Item 5 ) -------------------------------------------- [02/01/13]
From: [ Aleksander Koter of Evatronix SA ]
Subject: An AMS designer's report on the 2012 MunEDA Users Group meeting
Hi, John,
At the end of October, I attended the 7th MunEDA User Group Meeting (MUGM)
2012 in Munich. I'm an AMS design engineer at Evatronix in Warsaw. I work
at an IP design house in Poland that develops digital and mixed-signal IP
like as USB controllers, memory controllers, multimedia IP, and low power
microcontrollers plus their software and applications environments.
We started using WicKed this year. Two other co-workers and I went to this
MUGM. We were impressed by its scope: IP porting, circuit analysis,
modeling and optimization with MunEDA tools.
MUGM'12 was a two day open event with 25 technical presentations including
16 user reports from customers. We met about 80 participants, majority of
them from Europe -- but there were some people traveling from U.S., Brasil,
Malaysia, Korea and Japan.
- Agilent demoed their new GoldenGate/WiCkeD integration in their booth.
I appreciate when EDA vendors work together, especially in RF area.
- GlobalFoundries gave a speech about their process technologies and
how GF cooperates with MunEDA to support joint customers.
- TU Dresden showed MunEDA tools for standard cells (automated sizing
plus generating data for AOCV tables), post-layout optimization of
sense amplifiers, parasitic sensitivity calculation, and optimization
of clock amplifiers for 90 Gbits on-chip links in a SoC migration
from 65 nm TSMC to 28 nm GlobalFoundries process technology.
- Infineon showed how they use WiCkeD's optimizers to generate
physically reasonable and non-pessimistic process corner models for
automotive chips. They reported ~25% less error between corner
simulations and specification.
- Elena Raciti from STmicroelectronics discussed their tool flow for
statistical analysis with fast SPICE simulators. They use WiCkeD
with Mentor Eldo, Synopsys CustomSim XA and Cadence Virtuoso for
post-layout statistical analysis of large (~4 K MOS) timing control
circuits in 55 nm NVM process. Statistics of ~120 performance
metrics are required, and neither SPICE simulator can do that alone:
a full SPICE Monte Carlo run would take 16 days with 3000 samples
each 8 min, but the fast SPICE accuracy varies too much during
Monte Carlo (up to 10% max error on the golden references), where
run time was reduced to 2 days. With WiCkeD they solved it, as it
can do multiple simulators simultaneously, running fast SPICE Monte
Carlo and validate parts intelligently with the golden reference
simulator. Elena concluded her report that they consider this
methodology a "must-have" for large circuit statistical validation,
and it's deployed in their automotive microcontroller & RF division.
- STmicroelectronics also showed optimization of highly reliable std
cells with aging models for automotive chips, and a design time
reduction when automatically sizing LPDDR3 IOs in 28 nm FDSOI.
Reported getting ~35% better timing, while keeping to other specs.
- Altera showed WiCked batch-mode optimization of FPGA cells, routing
drivers and delay chains. Got 3% to 5% faster delay, better balance
between rise and fall times, with area down 9%-15% -- considering
all process corners and operation conditions.
- My colleague Carsten Elgert talked about our first experiences with
WiCkeD. We use WiCkeD with Cadence Spectre to analyse and optimize
eye diagrams in a dual speed USB differential signal receiver in
40 nm TSMC. We were pleasantly surprised how easy it was to retarget
our existing IP in IBM 180 nm to TSMC 40 nm with WiCkeD. We liked
the structured sizing flow in a design history and a nice results
presentation form in WiCkeD. Liked the WicKed Optimization Tool,
with optimization algorithms that we have never seen before.
We are not using WiCkeD in most efficient way, because of our first
steps learning curve limits, but estimate we finally speed up our
development by roughly 20%.
On our wishlist is a deeper integration into Cadence ADE; MunEDA is
working on that and showed us a beta version with many improvements.
- STARC Japan presented their new AMS Flow with WiCkeD SPT to migrate
Virtuoso schematics 63% faster and safely between PDKs, before
resizing blocks in the target PDK using WiCkeD's optimizers. (We
use the SPT schematic migration tool, too, and it works fine for us.)
- Fraunhofer optimized a high-performance digitally assisted LNA
that had ~100 performance specs to meet.
- Microsemi's SOC and FPGA specialist Marcel Derevlean showed sense
amplifier optimization for offset, speed, input cap and power. Was
a redesign to increase speed and yield for a product 65 nm SRAM.
Used WiCkeD to run Sensitivity Analysis, Monte Carlo and Worst-Case
analysis, plus WiCkeD optimizers that improve performance/yield of
the sense amplifier. Impressive to see how well their optimization
tools could improve offset variation of the sense amp in layout
extracted HSPICE netlists by 40%, while keeping all other specs.
The silicon is available and shows good SRAM yield on par with their
most recent products. In comparison, Marcel stated that the whole
yield optimization with WiCkeD took a day compared to at least
two weeks estimated manual design.
If you go to the MunEDA web page you can download the 600+ slides for the
user talks and tutorials shown at MUGM'12.
My co-workers and I highly recommend visiting the next MunEDA User Group
Meeting.
- Aleksander Koter
Evatronix SA Warsaw, Poland
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