( ESNUG 519 Item 4 ) -------------------------------------------- [02/14/13]
From: [ John Weiland of Abraxas ]
Subject: ARM, Nangate, Synopsys, Aragio, Tela, SypherMedia std cell libs
Hi, John,
ARM sells standard cell and IO libraries for 17 different foundries. Their
web site said feature sizes range from 250 nm to 22 nm, but the guy at the
DAC booth said they are still working on the 20/22 nm libraries with the
foundries.
The guy from Sagantec said that at 20/22 nm it takes about four times as
long to lay out as standard cell, because the design rules are so complex,
and I heard that rather than giving their layout folks design rules listing
what is not allowed, ARM is giving them 20-30 allowable geometries and
everything must be created from those.
Nangate, which had representatives at the Si2 booth, provides Mega Libraries
that contain 10,000 to 50,000 cells and a huge variety of drive strengths,
including multi-Vt and long gate versions of cells. They say long gate
cells are better than low Vt cells at low supply voltages. They claim the
large variety of cells can result in up to a 14% speed increase for some
designs, and can also benefit area and power. Nangate donated some libs to
Si2 and they are often used for evaluations.
Synopsys sells libraries with feature sizes down to 28 nm (at TSMC). Cells
come in high speed, high density and ultra density versions. They also sell
"Power Optimization Kits" with power shutoff switches, retention flops,
level shifters, and circuits for back biasing.
Aragio sells IO libraries for 65 nm, 55 nm, 40 nm and 28 nm processes at
GlobalFoundries (and I'm guessing Samsung and IBM too). They say they are
particularly adept with ESD protection structures, which get harder as
feature sizes shrink, particularly for things like RF and analog pads.
Tela Innovations creates cell libraries for TSMC where all the lower layers
run on one direction only and are uniformly spaced -- they look like an
interference pattern where there are some missing pieces from the lines.
In fact they had a DARPA contract to explore mask-less fabrication; an
interferometer is used to create a regular pattern of lines on the wafer,
and an e-beam cuts the lines to make the cells and interconnect. Even with
less exotic processing, these types of shapes are a lot easier to resolve.
Tela was doing 22 nm in 2009 and this year they are doing a test chip with
11 nm half pitch and 8 nm shapes. One would think this lack of 2D freedom
would make the standard cells larger, but they have a special contact/gate
waiver from TSMC so they come out about the same size, and they claim the
easier routing of higher layers makes the overall design about 20% smaller.
In one test case they compared a normal "2D" library to their "1D" library
and found a block done with their library was 20% smaller, 40% faster and
got 11% better yield. Boeing tried their library at 45 nm SOI and found it
saved 30% in area. I suspect that in the future all libraries may look
like Tela’s; whether that will be good for Tela’s market share remains to
be seen. They have also been teamed with SMI (SypherMedia International)
who has created a Tela library that is extremely hard to reverse engineer;
most of the cells are almost identical except for subtle differences on a
variety of layers.
SypherMedia International sells cell libraries that are extremely hard to
reverse engineer. They've had meetings at DAC before but this is their
first year with a booth. When I first saw a layout that used one of the
SypherMedia libraries, I thought I was looking at some weird memory, then
I slowly noticed slight differences between cells. Differences are on 5
different mask layers and they say no one has been able to reverse
engineer the set top box components that use their library. They have
libraries for TSMC's 40 nm process and the 90 m and 65 nm processes at IBM.
Obviously, anyone who gets the mask data will still be able to reverse
engineer; this just makes optical inspection of the part very hard.
- John Weiland
Abraxas Corp. Columbia, MD
Join
Index
Next->Item
|
|
