( ESNUG 521 Item 7 ) -------------------------------------------- [03/28/13]
From: [ John Weiland of Abraxas ]
Subject: Xilinx Vivado, Synplify, Certify, Precision RTL, Flexras, Menta
Hi, John,
In a world with ever fewer ASICs and ever more FPGAs, one of the scary
things for EDA companies is that tools from the FPGA vendors themselves
have historically been free or very cheap (subsidized by the cost of
the FPGA).
As a result, FPGA users gasp at tool prices that would not make an ASIC
designer blink. Some really good FPGA tools are just unsellable because
the cost is out of the FPGA designer’s expected price range.
I think that the legacy of free tools and burn-and-churn debug will haunt
FPGAs for years. The latest Xilinx part has 20 million equivalent ASIC
gates. Anyone who thinks they can use 2nd rate tools and slipshod
techniques for a design that large because they can program it over and
over again, will wind up programming it over and over and over and over
again and again and again, until whoever is paying their salary forces
them to use better tools and methodologies.
---- ---- ---- ---- ---- ---- ----
Shortly after DAC Xilinx began shipping their new Vivado tools suite,
which will replace their ISE suite. There will be a free web pack version
or the user can pay for the full suite. The new suite uses SDC instead of
their proprietary constraint format, IP-XACT for describing blocks instead
of their proprietary format, and it uses an IEEE standard for encryption.
Vivado also includes Atrenta Spyglass for linting and other checks. I would
be interested in pricing and restrictions, given that Spyglass tends to be
more expensive than what FPGA designers are used to spending.
The Artix-7 line from Xilinx apparently replaces their Spartan-6 line for
low cost applications, and they have a new Kintex-7 line for moderate
performance, moderate cost applications that can’t justify high performance
Virtex-7 or Virtex-6 parts. Their largest Virtex-7 (they say 20 M ASIC
gates equivalent) is a 3D IC with 4 dice on an interposer (really more like
2 1/2 D), and they have another heterogeneous die stack with two FPGA dice
plus a 28 Gbps transceiver manufactured using a different process.
---- ---- ---- ---- ---- ---- ----
Synopsys/Synplicity claims their Synplify tool is the most widely used FPGA
synthesis tool. It had four flavors but they have kept only the middle two.
Synplify Pro allows mixed languages, has RTL debug, graphical FSM design,
register retiming and ties to specific FPGA vendors. Synplify Premier adds
RTL instrumentation and debug of live, running FPGAs, compatibility with
Synopsys DesignWare, fault-tolerant FSM's and physical synthesis. Synplify
Premier with Design Planning adds physical design for Xilinx & Altera FPGAs.
Synopsys sells Identify for debugging your RTL in actual FPGA hardware. It
allows you to mark signals in the RTL as probes and set breakpoints, then
run the device and collect waveforms and monitor values on nets. They claim
the adding a new probe is fast because they use incremental compilation.
Identify Pro monitors FPGA hardware for error conditions, captures all the
stimulus leading to that error, and produce a testbench to reproduce the
error in RTL.
Synopsys also sells Certify, which partitions an ASIC prototype onto multiple
FPGAs and does automatic multiplexing of pins, insertion of probes, and
handling of ASIC-specific structures like clock trees.
---- ---- ---- ---- ---- ---- ----
Mentor sells FPGA tools. Leonardo Spectrum is their older synthesis tool,
but is advertized for ASIC synthesis as well as FPGA-to-ASIC methodology.
Precision RTL is a newer FPGA synthesis tool that supports System Verilog,
SDC, retiming and has support for DesignWare when doing ASIC prototyping.
Precision RTL Plus has physically aware synthesis with incremental synthesis
and low power optimizations (FPGA clock gating, intelligent RAM, burying hi
toggle nodes in LUTs, etc.), and includes IP blocks (like DesignWare) that
are not tied to any FPGA vendor.
Precision Physical does actual physical synthesis with interactive placement
optimization.
Mentor Precision Hi-Rel is Precision RTL Plus, plus addition features for
handling radiation induced single event effects/upsets (i.e. some gamma ray
or particle hits the chip and causes a register to change state). It has
some interesting finite state machine (FSM) synthesis options. The most
basic is making sure the FSM can’t get stuck in invalid states forever; if
the FSM gets into one it will come back out. They also have the option of
FSM implementations that will know if an SEU changed the FSM from one valid
state to another valid state, and implementations where all states one bit
away are considered the same state so single bit flips are tolerated
(obviously, this adds quite a bit of hardware to the FSM). Unlike their
competitors, they do not use one-hot encoding to do this. Precision Hi-Rel
also provides triple redundant voting similar to Xilinx XMR.
Mentor IO Designer facilitates codesign of FPGAs and boards. They claim that
the combination of their ReqTracer tool and FormalPro can prevent anything
bogus from showing up in a design.
Mentor was teamed with Auspy that sells a tool for partitioning an ASIC into
several FPGAs for prototyping, similar to the Synopsys/Synplicity Certify
tool; I’m not sure it that's still true.
---- ---- ---- ---- ---- ---- ----
Cadence sells Allegro FPGA System Planner, which allows codesign of FPGAs
and boards and understands FPGA pin assignment rules.
---- ---- ---- ---- ---- ---- ----
French company Flexras attended DAC for the first time. Their tool is Wasga
(sorry, that just does not sound French to me.) It partitions a large
design into multiple FPGAs like the Synplicity Certify tool. They claim the
designs produced by their tool will operate up to 10X faster because of
superior partitioning and that the tool has "unlimited capacity".
---- ---- ---- ---- ---- ---- ----
Menta sells embedded FPGA IP for use in ASICs and ASSPs. It is a soft core;
the IP is RTL with a ton of multiplexing. I don’t know what kind of speed
and area hit one would face by using a place and route tool to do the muxing
in an FPGA. They provide the tools for mapping, place and route.
Space-based systems have to use one time programmable anti-fuse based FPGAs
because of radiation concerns. Unfortunately this means the usual burn and
churn debug of the design can get really expensive, since each part can be
programmed only once.
---- ---- ---- ---- ---- ---- ----
Aldec offers adapter boards so a design can be debugged using a flash-based
FPGA, then the anti-fuse-based one can be swapped in once it is working.
- John Weiland
Abraxas Corp. Columbia, MD
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