( ESNUG 522 Item 4 ) -------------------------------------------- [04/18/13]
From: [ Jim Hogan of Vista Ventures LLC ]
Subject: Hogan compares Palladium, Veloce, EVE ZeBu, Aldec, Bluespec, Dini
Hi, John,
Below I have mapped top-level information for each vendor, according to the
emulation metrics I mentioned earlier. I derived the information for the
snapshot below from each vendor's website plus my general accumulated
knowledge to date.
- Category 1. Emulators are based on application-specific
processors. Cadence Palladium's processor is implemented
in an ASIC-structured custom fabric. Mentor Veloce's
processor is implemented in a custom FPGA fabric.
- Category 2. Emulation with a standard FPGA product at its
core. Synopsys-EVE is currently the player in this sector.
- Category 3. Other emulators with HW based on a standard
FPGA product. The primary differentiator between category
2 and 3 is capacity; however, there are other differences
as shown below. Aldec, Bluespec, Cadence RPP, Dini Group,
S2C, and HyperSilicon are primary vendors in this segment.
The emulator best suited to the designer problem is defined by what problem
they are trying to solve.
Source: EVE, Embedded Computing, 2010
The optimal choice lies in the intersection of a number of factors, with one
example outlined above.
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Emulation Vendors
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Cadence Palladium, Mentor Veloce
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Synopsys EVE Zebu
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Other: Aldec, Bluespec, Cadence RPP, HyperSilicon
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Emulator Architecture
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custom silicon, custom board, custom box (32 M to 2 B)
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off-the-shelf FPGA, custom board, custom box (25 M - 200 M)
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off-the-shelf FPGA, off-the-shelf board, off the shelf box (2 M - 50 M)
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Price/gate
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2-5 cents
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0.5 - 2 cents
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0.25 -1 cent
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Dedicated Support
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yes
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mixed
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no
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Design Capacity
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Claims up to 2 billion. Typical usage 100 M to 1 B gates.
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Claims up to 1 billion. Typical usage 25 M to 200 M gates.
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Claims up to 50+ million. Typical usage 2 M to 25 M gates.
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Primary Target Designs
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SoCs 100 M to 1 B gates. Large CPUs, GPUs, multi-chip systems, application processors.
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SoCs from 25 M to 200 M gates
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IP blocks, sub-system, and SoCs from 2 M to 25 M
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Speed range (cycles/sec)
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100 K to 2 M
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500 K to 5 M
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500 K to 20 M
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Compile time
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10-30 M gates/hour. Single workstation (Palladium). PC farm (Veloce). Includes automated partitioning time. Parallelizable: Yes
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25 M - 100 M gates/hr for PC farm. Proprietary software for fast FPGA partitioning, synthesis and P&R. Parallelizable: Yes
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1 M - 15 M gates/hr for PC farm. Constrained by FPGA vendor synthesis and P&R times. Doesn't include partitioning time. Parallelizable: Yes
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Partitioning
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automated
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automated
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semi-automated. Partitioning depends on # of FPGAs. Time range 30 min to 4 hours.
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Visibility
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full visibility. at-speed probe capture.
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static, dynamic probes. at-speed probe capture.
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static, dynamic probes (vendor dependent). at-speed probe capture (vendor dependent).
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Debug
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Breakpoints, assertions, simulation hot-swap, SW debug.
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Breakpoints, assertions, simulation hot-swap, SW debug.
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Breakpoints, assertions, simulation hot-swap, SW debug.
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Virtual platform API
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Yes
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Yes
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varies by vendor
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Transactor Availability
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Standard/off-the-shelf: Good. Custom: developed ad hoc
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Standard/off-the-shelf: Good. Custom: developed ad hoc
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Standard/off-the-shelf: Mixed. Custom: developed ad hoc
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Verification Language - Native support
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C++, SystemC, Specman e, SystemVerilog, OVM, SVA, PSL, OVL
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Synthesizable Verilog, VHDL, System Verilog
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Synthesizable Verilog, VHDL, System Verilog
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Memory
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up to 1 TB
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up to 200 GB
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up to 32 GB
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Users
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1 to 512 users
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1 to 49
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1 user
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Here is my quick summary of the different emulation vendors for 2013.
Category 1:
- Cadence Palladium. Hats off to Cadence for being pioneers in
emulation and sustaining innovation to maintain a very competitive
product year-over-year.
- Mentor Veloce. Their revenue numbers show emulation is a growing
segment for them. (See ESNUG 510 #7.) Clearly Wally and Greg
have been investing heavily in emulation.
Category 2:
- Synopsys EVE Zebu. This has been the choice for companies and
design groups doing mid-size SoCs or blocks for emulation. It
is no secret that Intel was an EVE customer. (See ESNUG 508 #6.)
My expectation is that with the Synopsys acquisition, EVE will now
move upstream to challenge Cadence and Mentor at the high end.
Category 3:
- Aldec HES-DVM. The company initially grew out of providing system
emulation/simulation using FPGAs for eventual implementation in
FPGAs. FPGAs will continue to be a choice for system designers
with low volumes, including the mil-aero world. Will they try
to move into the SoC market?
- Bluespec Semu. Bluespec expanded their emulation footprint in
March with a new FPGA-based desktop form factor verification and
hybrid emulator. They emphasize low cost, ease of use, fast
deployment using third-party FPGA boards, dynamic hardware debug
(no re-instrument and re-synthesis) and a C API to integrate
SystemC/C/C++ models and test benches. Bluespec claims to need
only 1 day set up.
- Cadence RPP. The Cadence FPGA-based Rapid Prototyping Platform
is an FPGA-based prototyper for early software development and
high-performance system validation. While not positioned as an
emulator (See ESNUG 517 #6) it uses the core technology
of FPGA-based emulators and confirms the need for boxes with
higher performance and lower cost than processor-based emulators
for pre-silicon software development.
- The Dini Group. An established leader in FPGA boards for
prototyping and emulation. The Dini Group consistently delivers
high quality, high capacity boards with the shortest time-to-market
for leading edge FPGAs.
- S2C. Offers FPGA boards and software and IP for system-level
design verification and acceleration. Their new boards based on
14 M gate Xilinx FPGAs.
- HyperSilicon. Company to watch from mainland China, focusing on
FPGA prototyping boards. Offers boards similar to S2C.
My conclusion is that emulation has indeed gone mainstream. Its growth
extends from the rise of the SoC as the cornerstone of system hardware,
with its associated multiple SW functions. What's also helped emulation
grow is its better debug, increased FPGA sizes, and its newer ability to
handle complex designs.
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The reason for my report was to analyze the segment and try to put some
order to the market place. I'm not the only source of info on this. I'd
like to invite the DeepChip readers to feel free to add their perspective
and to update the charts and data I have gathered.
- Jim Hogan
Vista Ventures, LLC Los Gatos, CA
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