( ESNUG 527 Item 1 ) -------------------------------------------- [07/11/13]
From: [ Trent McConaghy of Solido Design ]
Subject: Trent on DAC'13 papers on Moore's Law, FinFETs, and futures
Hi, John,
Here's my take on the 28 analog/custom design papers and tutorials that I
saw at the recent Austin DAC. I focused on these because it's what we do.
These 6 papers are on Moore's Law, FinFETs, and futures.
- Trent McConaghy, CTO
Solido Design Automation Vancouver, Canada
---- ---- ---- ---- ---- ---- ----
Paper: TEASE - A Systematic Analysis Framework for Early Evaluation
of FinFET-based Advanced Technology Nodes
Authors: Arindam Mallik et al. (IMEC)
From the 12 IMEC authors in the introduction of their paper:
"Maintaining silicon yield has been the major bottleneck for
successful technology scaling in the future as the cost
benefit outlined by Moore has rapidly eroded."
The authors identify the yield culprits as a sharp increase in the number
of systematic layout geometry-induced faults and "process variability."
They explore and optimize nodes using std cell performance as a surrogate.
Their TEASE framework combines lithography and electrical constraints,
optimizing a few representative standard cells, using mostly standard EDA
tools.
Using their TEASE framework, the authors identify promising optimizations
for standard cell layouts, such as:
- Using the local interconnect layers more aggressively
for routing (20% less area)
- Using a gridded unidirectional metal (20% less area, 8%
slower)
- Compared to dual fins, one-fin designs are 33% less area
but 44% slower.
Notably, their TEASE framework can be used to detect which constraints that
bottleneck advanced node design enablement.
---- ---- ---- ---- ---- ---- ----
Paper: Predicting Future Product Performance: Modeling and Evaluation
of Standard Cells in FinFET Technologies
Authors: Veit Kleeberger, Helmut Graeb, and Ulf Schlichtmann (TU Munich)
Exploring the potential of FinFETs is a hot topic; measuring standard cell
performance is a useful surrogate, as the IMEC research showed. Whereas the
IMEC folks focused on standard cell layout, the authors focus on standard
cell *sizing* to assess FinFET technology node performance.
The methodology was to start with predictive technology models from Kevin
Cao's ASU team, and include FinFET process variation (including variation in
fin thickness and fin height) and aging effects. To ensure that a given
cell had best possible performance, they performed automated variation-aware
sizing. The authors then systematically compared the effect of the
following items in terms of their impact on standard cell performance
(delay, 1/slope, leakage).
a) planar CMOS vs. FinFET
b) global process variation
c) local process variation
d) environmental variation
e) aging
The authors found that all five factors had a measurable effect, depending
on the circuit and the performance measure.
---- ---- ---- ---- ---- ---- ----
Paper: The ITRS Design Technology and System Drivers Roadmap;
Process and Status
Author: Andrew Khang (UC San Diego)
Andrew Khang has contributed to the ITRS Design Technology component for
10+ years, so he is well-situated to give this overview. A few takeaways:
1) Metrics. "What cannot be measured cannot be tracked or improved".
Much of the paper was about identifying the emerging challenges
and then the appropriate metrics to track / schedule progress, and
in some cases identifying which metrics which should be retired.
2) "Shared red bricks." Red bricks are potential showstoppers, and
the idea of sharing them means that everyone agrees on them, and
that solutions can come from many places: process innovation,
device design, circuit design, design tools, and system design.
3) Design Cost Model. Since 2001, this model encompasses both
hardware and software development costs, and "quantifies the
impact of design technology innovation. For example, the
hardware design costs for a consumer portable SOC design in 2011
are estimated at $25.7 M, compared with an estimated $7,708 M had
design technology innovations between 1993 and 2009 not
occurred (!)
4) Key messages. New key messages include:
i. focus at the design-manufacturing interface has evolved
from 'manufacturability' to a more general 'variability'
ii. design technology innovations must keep on schedule through
the end of the roadmap in order to contain power.
5) Variability. The 2009 Design Chapter added projections for
circuit-level impacts for variability, focusing on three
canonical circuits -- the SRAM bitcell, latch, and inverter. The
2011 ITRS observed that "SRAM failure rate has already become a
significant problem in the current technology node" and that the
latch "is predicted to be problematic by the 20nm foundry node".
Analysis showed that larger circuits or higher Vdd control
variability, but of course that defeats the purpose of scaling.
6) ITRS is not perfect. The pre-2001 ITRS frequency scaling
prediction was 41%/year. In 2001, it was modified to 17%/year;
in 2007, 8%/year; in 2011, 4%/year. These changes illuminate the
difficulty of writing the ITRS, and the courage it takes to
commit to paper such an influential agenda.
---- ---- ---- ---- ---- ---- ----
Paper: Reliable On-Chip Systems in the Nano-Era: Lessons Learnt
and Future Trends
Authors: Jorg Henkel et al. (KIT Karlsruhe, UC Irvine, UCLA,
IBM Austin, Uni Kaiserslautern)
This paper is has researchers from many different institutions, giving
various perspectives on reliability issues and how to address these issues.
The issues are well-known by now: "soft errors" (process variation),
"aging", and "impact of temperature" (higher temperature accelerates aging).
The researchers note a particular problem for SRAM variability: soft error
rate of bitcells decreased by 2x going from 130nm to 65nm, but the memory
capacity increased by more than 2x, leading to an overall higher memory
system failure rate. Also, multiple cell upsets (MCUs), where more than one
bit fails, is now sufficiently common that it must be factored into
calculations (or risk optimistic error rates). Research in variability /
reliability handling includes:
- hardware-level mitigation like error correction,
- OS-level thermal management,
- software-level mitigation, and
- application-specific improvements like letting video quality
degrade as needed to maintain power consumption.
Perspectives to improve reliability include: jointly optimizing across >1
design layers, run-time sensing and adaptation / "cyberphysical" approach,
exploiting application resilience, CAD for reliability, and process scaling
including resilience cost reductions (so that the economics of smaller nodes
works out).
---- ---- ---- ---- ---- ---- ----
Paper: Predicting Future Technology Performance
Authors: by Asen Asenov et al. (Gold Standard Simulations, U. of Glasgow)
In the last couple years, the authors have been analyzing FinFET device
behavior using their 3D "atomistic" TCAD device simulator GARAND. Their DAC
paper this year continues that research thread. The research analyzes the
potential benefits of "high-mobility" channel materials on FinFET devices,
i.e. replacing silicon channels with III-Vs and Germanium materials.
To perform such analyses places particular demands on TCAD tools; the status
quo approach of "drift diffusion" (DD) is not accurate enough, and the
status quo approach of "fully quantum simulation" is too slow.
The authors extend GARAND with 3D "Ensemble Monte Carlo" (EMC) simulations
which balance speed vs. accuracy, allowing them to analyze high-mobility
channel materials. Using GARAND EMC, the authors conclusively show the
benefits of these "high-mobility" materials.
---- ---- ---- ---- ---- ---- ----
Paper: Exploring Tunnel-FET for Ultra Low Power Analog Applications:
A Case Study on Operational Transconductance Amplifier
Authors: Amit Ranjan Trivedi et al. (Georgia Tech)
Chenming Hu, the father of the FinFET, has publicly stated that FinFETs are
good for analog. But it's getting more specific now, such as this year's
DAC paper by these Georgia Tech researchers. To be able to even consider
FinFET design, the researchers use the ASU Predictive Technology Models for
FinFETs. The researchers were able to design FinFET-based OTAs with
promising simulation performance numbers, despite some special FinFET
challenges such as higher Shot noise at lower biasing current. I'd love to
see the silicon numbers.
Join
Index
Next->Item
|
|
