( ESNUG 527 Item 6 ) -------------------------------------------- [07/11/13]
From: [ Trent McConaghy of Solido Design ]
Subject: Trent on DAC'13 tutorials, Gary Smith, custom IC EDA vendors
Hi, John,
Here's the two tutorials, Gary Smith stuff, and EDA vendors that had to do
with analog/custom design.
- Trent McConaghy, CTO
Solido Design Automation Vancouver, Canada
---- ---- ---- ---- ---- ---- ----
DAC had two tutorials related to custom design.
Tutorial: Modeling, Abstraction and Verification of Non-Volatile Memories
The tutorial reviews new techniques for formal functional verification of
non-volatile memories (Flash, MRAM, FeRAM, etc). The two speakers were
Sandip Ray (Intel) and Jay Bhadra (Freescale).
---- ---- ---- ---- ---- ---- ----
Tutorial: Winning in Monte Carlo: Managing Simulations under Variability
and Reliability
The four technical speakers were/said:
- Georges Gielen (from KU Leuven) discussed variability and
reliability issues for analog design, and how they might be
handled via CAD and circuit design.
- Yu "Kevin" Cao (from ASU) discussed variability and reliability
issues for digital design, and how CAD can help. He also compared
planar CMOS vs. FinFET variation, leveraging his long-running
research on predictive technology models (PTMs).
- Trent McConaghy (myself from Solido) described industrial
techniques for fast PVT, 3-sigma Monte Carlo, and high-sigma Monte
Carlo verification.
- Ting Ku (from Nvidia) described a signal integrity case study
using variation-aware design techniques, using Solido tools.
---- ---- ---- ---- ---- ---- ----
GARY SMITH:
As usual, EDA analyst Gary Smith presented his "What to See @ DAC" list.
Gary covered the big digital topics of ESL (Electronic System Level) and RTL
(Register Transfer Level).
Gary then discussed custom design, using a subtitle "It's the Transistors
Stupid!". Gary listed three transistor players on his What To See List.
Here is what he said about them.
1. Solido Design Automation.
"Solido lets you simulate a lot of transistors...Solido is going
to be a major major tool at 20nm and 14nm".(Solido's customers
are indeed using Variation Designer in production at 20nm, 16nm,
and 14nm.)
2. Proplus Design Solutions.
"ProPlus is the new guy that gives you a decent yield". ProPlus
is ex-Celestry / ex-Cadence folks, taking on Synopsys, Cadence
and Berkeley DA simulators with a variation twist.
3. Sage Design Automation.
"Sage gives you a handle on the DRC mess". Sage DA auto-extracts
design rules, because manual design of such rules at deep
submicron nodes is painful and suboptimal. Sage is led by Coby
Zelnick, who was previously CEO of Sagantec.
Gary also included four other custom CAD companies:
1. Berkeley Design Automation,
BDA just release their new Analog Characterization Environment.
2. JEDAT (Japan EDA Technologies)
JEDAT just released an OpenAccess based schematic+layout
environment tool for DAC 2013;
3. Tanner EDA
Tanner is "challenging the Big Guys" by focusing its schematic
+ layout more on ASIC designers
4. Library Technologies.
aka "Mehmet's Low Power Libraries".
---- ---- ---- ---- ---- ---- ----
CUSTOM IC CAD VENDORS:
Below are the custom IC CAD vendors that I noticed exhibiting at Austin DAC.
As per Solido company policy to be completely vendor neutral, each specific
tool is listed by alphabetical order.
Front-End Environment:
AnalogRails FrontEnd
Berkeley Design Automation Analog Characterization Environment (ACE)
Cadence Virtuoso Analog Design Environment
JEDAT Circuit Cube
Mentor Graphics Pyxis Schematic
Symica DE
Synopsys Galaxy Custom Designer SE
Tanner HiPer Simulation
SPICE Simulation:
Berkeley Design Automation Analog FastSPICE
Cadence Spectre, SpectreRF, APS, UltraSim
Mentor Graphics Eldo Classic, Eldo Premier, Eldo RF
Proplus NanoSpice
Symica SymSpice
Synopsys HSPICE, HSIM, CustomSim, XA, FineSim
Tanner HiPer Simulation, HiPer Simulation AFS
Variation Design:
Infiniscale Iclys
Muneda Wicked
Proplus Nanoyield
Solido Design Automation Variation Designer (my company)
Fast Behavioral Model Simulation:
Asygn Tactyle, Fasyle
Netlist-to-Behavioral Models:
Orora Arana
Netlist-to-Schematic:
Concept Engineering T-engine
Library Characterization:
Cadence Virtuoso Liberate
CLK Design Automatin AOCV FX
G-Analog Design Automation Gchar
IROC Technologies TFIT
Nangate Library Creator
Synopsys SiliconSmart, Liberty NCX
Back-End Environment:
AnalogRails Premium
Cadence Virtuoso Layout Suite
JEDAT Ismo
Mentor Graphics Pyxis Layout
SkillCAD IC Layout Automation Suite
Symica SymLayout
Synopsys Galaxy Custom Designer LE
Tanner L-Edit Router
Design Rule Extraction:
Sage Design Automation iDRM
Parasitic Extraction:
Cadence QRC Extraction
Edxact Jivaco
Mentor Graphics Calibre
Pulsic Unity
Silicon Frontline F3D
Synopsys StarRC
Automated Place and Route:
AnalogRails Premium
Cadence Virtuoso Layout Suite
JEDAT Pathmo, Rexsir
SkillCAD IC Layout Automation Suite
I wrote this was a guide to those analog/custom designers who couldn't have
attended DAC. I hope they find it helpful.
- Trent McConaghy, CTO
Solido Design Automation Vancouver, Canada
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