( ESNUG 529 Item 3 ) -------------------------------------------- [07/18/13]

Subject: Verilog/VHDL RTL, SystemC, sign-off, Catapult, middleware, AutoESL




     




                DAC'13 Troublemaker's Panel in Austin, TX

     Gary Smith - olde school Verilog/VHDL RTL designers are NOT making
     the transition to SystemC/C++ based design.  It's only the young
     kids graduating from college who are now that are doing it.  The
     reason why is most IP is in Verilog/VHDL RTL.  Also universities
     are not training enough middleware engineers.  There's a shortage
     of SW apps writers who understand HW.

     Joe Costello - Verilog/VHDL RTL is the new netlist.  In the future
     chip designs will be signed-off in RTL.  Oasys does well because
     this being the trend.

     Joe Sawicki - Mentor divested CatapultC into Calypto so that it
     could get verification in it.  It's been doing well, but the fact
     that there isn't a lot of SystemC IP around holds everyone back.

     Mike Gianfagna - Atrenta tried to sell SystemC/C++ linting tools
     but no one wanted them.  Designers distrust the machine generated
     RTL that comes out of SystemC/C++ synthesis.  Slow adoption.

     Jim Hogan - I didn't invest in SystemC/C++, but I did invest in
     behavioral synthesis with AutoESL.  That sold to Xilinx for $25
     million -- a good return!  SoC's are now a collection of IP
     blocks.  No one want to go down to transistors if they can
     avoid it.

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)