| Customer
| Presentation Title
and link
| Event/Source
| Results
|
| Advantest
| Unique approach of using Palladium XP to speed up simulation of analog/full custom netlist
| CDNLive EMEA 2013
| 50x acceleration compared to analog simulation
|
| Altair
| Slides 26-28 in in Hardware / Software Co-Development using the System Development Suite
| CDNLive Israel 2012
| Comparison of RTL Sim+ISS, Custom FPGA boards, Rapid FPGA Based Prototype and Palladium Emulation
|
| AMD
| Enabling a New Paradigm of System-Level Debug Productivity While Maintaining Full In-Circuit Emulation Performance
| CDNLive 2012
| Significantly reduce testplan execution time; Increase confidence in design health; Improve infrastructure readiness pre-silicon
|
| AMD
| Palladium Usage at AMD
| Video - 2012
| Alex Starr, Hardware Emulation Architect at AMD, highlights the unique capabilities of Palladium XP and in-circuit acceleration
|
| AMD
| A new paradigm for system-level debug productivity
| DAC 2012
| From and internal customer at AMD: "Just wanted to highlight another success story: Debug that would've been drawn out took under two hours to narrow down and form a theory, which took us to root cause in another hour."
|
| AMD
| Addressing Hardware/Software Co-Development, System Integration, and Time to Market
| DAC 2012
| Full Video of Alex Starr's presentation
|
| AMD
| Complementing In-Circuit Emulation with Virtualization for Improved Efficiency, Debug Productivity and Performance
| DAC 2013
| New and complementary usage models for emulation are emerging and becoming common practice. In-circuit emulation holds its position as a mainstay of emulation (Real-world traffic, real devices help get to early silicon success). Embedded target solutions are growing in popularity (Save/Restore is a key component to get deep into software workloads) and hybrid models can increase software workload performance dramatically (Can be used for specific, targeted testing)
|
| ARM
| Verifying Big.Little Using The Palladium XP
| CDNLive India 2012
| How Many Cycles are Needed to Verify ARM's big.LITTLE on Palladium XP?
|
| Bluespec (Partner)
| Bridging Virtual Platforms and FPGA-based Prototypes for Early, High-Speed, Accurate Software Development
| CDNLive EMEA 2013
| Connecting virtual Platforms and FPGA based prototyping
|
| Bluespec (Partner)
| The Best of Both Worlds -- Combining Virtual and FPGA-based Prototypes
| DAC 2013
| Connecting virtual Platforms and FPGA based prototyping
|
| Broadcom
| Low Power Verification And System Validation Using Common Power Intent
| CDNLive India 2012
| CPF power intent in emulation and simulation
|
| Broadcom
| Palladium Usage at Broadcom
| Video - 2013
| Vahid Ordoubadian, Director - Mobile Platform Group at Broadcom, describes the use of Cadence Palladium XP to validate a new architecture for a complex mobile SoC for mobile platform devices.
|
| Broadcom
| Transaction Based Acceleration -- Strong Ammunition in Any Verification Arsenal
| DVCon 2011
| 292x performance speed-up over RTl simulation
|
| Broadcom
| Faster System Bring-up with an Embedded Testbench on Palladium
| DAC 2013
| Fastest bring up ever for a new architecture
|
| Broadcom
| Broadcom Expands Use of Cadence
Verification Computing Platform to Tackle System Realization
| Feb 2011
| Our system designs are among the most complex in the industry, and the Cadence technologies -- both emulation and transaction-based acceleration -- provide the user controllability and real-world verification environments we need for system-level integration and early hardware/software system validation," said Neil Kim, executive vice president, Operations and Central Engineering, Broadcom Corporation. "The Palladium XP technology reduces time to market and improves quality."
|
| CSR
| Palladium XP experience in CSR
| CDNLive Israel 2012
| Software development, acceleration of hardware tests
|
| Freescale
| Fast Waveform Generation for Test Pattern Using Cadence Palladium
| CDNLive 2012
| Performance Improvement: Time to obtain waveform: 9.77x, Reduction in emulation run time: 43.28 x
|
| Freescale
| Palladium Usage at Freescale
| Video - 2012
| Wai-Chee Wong, Senior Member of Technical Staff at Freescale Semiconductor, details how Palladium XP helps speed their verification effort by 10,000x over simulation.
|
| Freescale
| Implementation of a Multi-threaded 64-bit Power Architecture Core on the RPP, FPGA-based Prototyping System
| CDNLive 2012
| Able to quickly run Coremark and many other benchmarks for
performance validation; Able to get performance metrics via the Nexus trace through the external DDR memory interface; Design changes for performance can be rebuilt for benchmarking in about a day or two; Software/compiler optimizations for benchmarks can be done and tested within minutes
|
| Freescale
| e6500 Power Architecture Development
| Video - 2013
| Hear from Michael Schinzler, Logic Designer at Freescale Semiconductor, as he highlights the use of the Cadence Rapid Prototyping Platform to help verify their e6500 Power Architecture Core.
|
| Freescale
| Case Study: Using Cadence Palladium for SoC Performance Validation and Analysis
| DAC 2013
| Performance validation and analysis is becoming more important because of the advancements in SOC and reuse methodology. Emulation is a good platform because of fast execution time as compared to simulation, full visibility of internal signals, and the fast turnaround time of model build. Mapping system level performance goals to SoC level is achievable. Once the mapping Sis done, the value of validating performance goal before tape out is extremely valuable.
|
| LeCroy (Partner)
| Ubiquitous PCI Express Verification from Simulation Thru Post-Silicon Development
| DAC 2012
| Connect your RTL design in Palladium to speed bridge, connect SpeedBridge to target system (a motherboard, live ethernet traffic, video camera etc), generate SimPASS trace file as your RTL runs in Palladium and load the trace files in SimPASS for graphical debug and analysis
|
| LSI
| A Deterministic Flow -- Combining Virtual Prototypes, Emulation and FPGA-Based Prototypes
| DAC 2012
| Reduced spins of the design, much faster chip-evaluation when silicon arrives and software ready to go Integration/System-Engineering team already up to speed on the device. Effective widening of the pre-silicon testing window.
|
| LSI
| Addressing Hardware/Software Co-Development, System Integration, and Time to Market
| DAC 2012
| Full Video of Chuck Cruse's presentation
|
| Mellanox
| Cadence Palladium XP Platform Chosen by Mellanox Technologies to Shorten Development Time of Interconnect Products
| August 2012
| "Mellanox chose Cadence's Palladium XP platform with PCI Express 3.0 and Ethernet SpeedBridge solutions to effectively accelerate our hardware and software integration while improving quality and performance metrics," said Roni Ashuri, senior vice president of engineering at Mellanox. "With the Palladium XP platform, we were able to speed up deployment of our interconnect products and achieve faster time to market."
|
| Mitsubishi
| Mentioned in Cadence Earnings Call
| July 2013
| "We were competitive in Ricoh and Mitsubishi Electric, and significantly increased our capacity growth in mobile and system customers."
|
| Microsoft
| Building Xbox One: An inside look at Microsoft's play for the next generation of gaming
| May 2013
| "The spaceship-like device originates from Cadence Design Systems, and serves to run a variety of processor emulations." [...] "Our friend the dolphin shows up once more on a monitor displaying what the emulator is up to."
|
Nethra
(No longer in business but a good ESNUG example from 2010)
| We switched to Palladium because of the following issues: (1) Our existing FPGA did not have enough capacity for our new designs. (2) Off the shelf FPGA boards did not have enough connectivity (3) Building a custom FPGA board would take some time.
| ESNUG 486
| "Ramp up time was very short - we got the box just before tape out and got it working and simulated our use cases before tape out."
|
| NVIDIA
| Sneak Peak inside NVIDIA's Emulation Lab
| May 2011
| "Today's GPUs, which are some of the world's most complex devices, have billions of transistors," said Narendra Konda, NVIDIA engineering and emulation lab director. "There's no way around the fact that cutting-edge design tools like hardware emulators are essential for designing, verifying, developing software drivers and integrating software and hardware components of GPUs and mobile processors."
|
| NVIDIA
| Palladium Usage at NVIDIA
| Video - 2012
| Narendra Konda, Director, HW Engineering at NVIDIA, discusses leveraging Palladium XP and the Rapid Prototyping Platform to integrate complex hardware and software designs.
|
| NVIDIA
| Palladium Usage at NVIDIA
| Video - 2011
| Narendra Konda, Director of Hardware Engineering at NVIDIA, outlines how the Cadence System Development Suite helps his design team successfully integrate complex hardware and software, develop app-ready systems more quickly, and ultimately improve the overall quality and competitiveness of their products.
|
| Nufront
| NS115 System Emulation Based on Cadence Palladium XP
| CDNLive China 2012
| Achieved 1000x performance improvement over RTL simulation;
Enabled early system-level integration and software validation (Android / Linux) with the emulated NS115;
correlated power consumption using realistic runtime environments and applications before silicon is available;
Fast turn around time greatly improve the efficiency of verification
|
| Panasonic
| Cadence Palladium XP Verification Computing Platform Speeds Deployment of Panasonic Systems-on-Chip for Digital Consumer Products
| December 2011
| "As digital consumer products become increasingly complex, so, too, does the verification of SoCs used to drive them," said Satoru Fujikawa, Director of the Digital Core Development Center, Panasonic Corporation. "The Palladium XP system has enabled us to validate our sophisticated SoC designs at the system level, accelerating chip level verification, predictably, and meeting our schedule requirements."
|
| PMC Sierra
| Functional Verification of Next Generation ICs with Next Generation Tools
| CDNLive 2012
| 40x acceleration
|
| PLX technologies
| "Quick turn-around time. Palladium has a very decent front-end synthesizer and compiler. It takes less than 30 minutes for 10-15 M gates to complete the cycle: Fix-RTL -> synthesize/compile -> rerun -> verify the fix."
| ESNUG 486
| "Time to bring up the platform is considerably shortened"
|
| Qualcomm
| Mentioned in Cadence Earnings Call
| April 2013
| "In Q1, our Palladium XP business was categorized by a number of significant repeat orders with leading semiconductor companies, including Qualcomm."
|
| Ricoh
| Ricoh Selects Cadence Palladium XP Platform for Next-Generation Multifunction Printer SoC Development
| July 2013
| "We chose the Palladium XP platform based on its superior technology, better value over alternative solutions and excellent technical support team," said Mr. Koichi Kamon, deputy division director of the Work Solutions Development Division at Ricoh. "The simulation acceleration bring-up time with the Palladium XP platform is by far the fastest and easiest in the industry, making it an easy choice for the SoC development of our state-of-the-art multifunction printer products."
|
| Rohde & Schwartz (Partner)
| LTE-Advanced with Palladium XP
| DAC 2012
| In conjunction with Cadence Palladium XP emulation platform a turnkey
solution to shorten time to market!
|
| Samsung
| Slides 31-33 in Hardware / Software Co-Development using the System Development Suite
| CDNLive Israel 2012
| Verify 5-32 Million Gates Image Signal Processing (ISP) Design, Comparison of Incisive, FPGA and Palladium
|
| Samsung
| PCIe Based SSD Verification Environment Using PCIe AVIP- Challenges Involved
| CDNLive India 2012
| 430x Speedup over pure RTL simulation
|
| Sandforce
| "I have used Palladium, and it is a tool which can carry it's weight in gold if you use it appropriately. The tool works best as an In-Circuit-Emulator (ICE)."
| ESNUG 486
| "I used it to prototype a video processing chip and was able to test out different architecture configurations for the product because of the way I modularized the synthesis and netlist creations. The prototype I was developing was able to communicate over PCI-E SpeedBridge and a real serial console to debug and communicate to the Palladium box.
|
| Sigma Design
| Accelerating Vector Driven Verilog Testbench Using Palladium XP
| CDNLive Israel 2012
| Hardware regressions and debug for networked home entertainment semiconductor solutions
|
| sTec
| Firmware Development and Pre-silicon Verification with FPGA-based Prototyping
| DAC 2013
| Overview how RTL Simulation, Emulation and FPGA Based Prototyping work together.
|
| STMicroelectronics
| Coverage Solutions On Palladium XP
| CDNLive India 2012
| Palladium-XP is able to support most of the SV functional coverage
constructs and toggle coverage; Coverage on Emulation without much penalty on performance & area
utilization.
|
Telegent
(No longer in business but a good ESNUG example from 2010)
| On FPGA and Processor Based Emulation: "Like real life, there were pluses and minuses to each approach; so we used both."
| ESNUG 486
| "The short story is Palladium
nicely bridges the gap b/w slow-but-flexible SW simulators (~10 KHz) and
the fast-but-inflexible FPGA platform (~100 MHz) by providing speeds of up
to 2 MHz plus the visibility and turn times of a software simulator. The
Palladium system enhances producitivity during debug when the hardware and firmware are being concurrently developed."
|
| Texas Instruments
| Low Power analysis with Palladium (DPA)
| December 2012
| "We continue to improve our power expectation, power estimation, and silicon measurement for our OMAP application processor. With Cadence Palladium XP Dynamic Power Analysis, combined with Encounter Power System, we achieved greater-than 90% accurate correlation between the architects' power estimation and actual silicon power consumption measurements, enabling us to deliver the best thermal and power experience to our customers."
|
| Xilinx
| Zynq -7000 Extensible Processing Platform From RTL to Success with Emulation
| DAC 2012
| "Emulation is a powerful tool - Has allowed us to find bugs early, has enabled us to track down issues much quicker than before, has empowered us to fix bugs and look for alternate implementations and plays an important in the post-silicon debug and verification process"
|
