( ESNUG 534 Item 1 ) -------------------------------------------- [11/08/13]
Editor's Note: I love user scoops like this! Looks like Cadence is
taking a 2nd run at Apache/Ansys in the IR-drop game. Scoop! - John
---- ---- ---- ---- ---- ---- ----
Subject: SCOOP -- User reviews new CDNS Voltus that takes on Apache Redhawk
> Ansys/Apache RedHawk DMP does full-chip power integrity analysis and
> sign-off, transients, simultaneous switching noise including package
> and PCB -- but it now has new distributed machine processing (DMP)
> that lets it 500 M+ gates, with the accuracy as flat analysis. DMP
> did ~2X runtime, ~2.5X less memory vs. flat simulation. Less than
> 2% accuracy loss, 60 M gates and 1.6 B design unknowns on 4 machines.
>
> - from http://www.deepchip.com/gadfly/gad053013.html
From: [ A Little Bird ]
Hi, John,
I know how you like scoops. Have fun.
We've been working with Cadence Voltus, their new unannounced cell-based
static/dynamic digital power analysis tool that replaces their present
Cadence EPS tool and directly competes against Apache/Ansys Redhawk.
We looked at Redhawk a few years ago and decided to not use it because it
couldn't handle our larger design sizes (over 200 M instances) but the newer
Cadence EPS could.
My comparison is of Cadence EPS (hierarchical) vs. Voltus (hierarchical).
Our old power analysis flow went as follows:
- VCS simulation
- PrimeTime STA
- Design Compiler converts Verilog to gates.
- Talus/ICC P&R
- Read design in gate form (.lib, LEF/DEF, Verilog, VCD files)
into EPS. EPS stitches everything together just like how
First Encounter does. EPS analyzes total power, static and
dynamic IR-drop, and does decap optimations. Gives users
the oil maps of IR-drop on the layout.
When all block layouts were assembled, EPS took over a week to analyze
power at the fullchip level. That throughput was not enough to meet our
tape-out schedule. We needed a tool which would handle 200+ M instances
with quick turnaround to analyze the effects of our last minute ECOs.
---- ---- ---- ---- ---- ---- ----
Our local Cadence support team gave us a beta version of Voltus.
It was a direct swap; took EPS out of our flow; put Voltus in its place.
The first big change is Cadence R&D got rid of EPS's 8 power grid views
and consolidated them down to 3 Voltus views:
Cadence EPS Views Voltus Views
----------------- ------------
Port Early
Detailed ---------------> IR
Reduced EM
Collapsed
Quick Detailed
Quick Reduced
Detailed Dynamic
Reduced Dynamic
Before, for rail analysis, EPS users had to switch by hand between these
8 power grid views. Now, with Voltus it's been condensed to two views:
- XD for accelerated definition and early implementation rail analysis
- HD for high definition and final verification IR/EM analysis
The other noticeable change was a huge improvement in runtime and multi-CPU
scalability for fullchip power and rail analysis. EPS ran 8 CPU's at most.
Voltus runs 32 CPU's. Voltus got us a 9X runtime speed-up vs. EPS.
Tool Fullchip Static/Dynamic Analysis for TSMC 20 nm
----- ------------------------------------------------
Cadence EPS 8-10 days (8 CPUs)
Cadence Voltus 26 hrs (32 CPUs)
Apache Redhawk can't do 200+ instances
These runtimes includes static- and dynamic- power, and rail-analysis time
for the VDD/GND nets. With a day of turnaround time, we could do more
power analysis runs on this design than we have ever done on any other
design in the past.
Some of the extra runs we did to correlate the accuracy of the new Voltus
release vs EPS. We validated the worstcase IR-drop plots coming out of
dynamic rail analysis. The IR-drop ranges correlated with 5% of EPS.
Worstcase IR-drop were all within 1 mV.
Like big chips being designed everywhere else, we had power-gated blocks,
complex clocking (with clock gates); plus a tiny bit of asynch logic;
and Voltus seemed to handle it the same as EPS. Had no surprises there.
---- ---- ---- ---- ---- ---- ----
WHAT NEEDS IMPROVEMENT:
- Its simplified library generation with hierarchical PGVs makes
Voltus setup a bit easier, but they need to simplify the flows
further. Their hierarchical view generation is sometimes a
very tedious process where we have to define all the partition
hierarchies manually.
- We were able to generate power-grid views for std cells, memories
and I/Os and use them in Voltus. While this gave us a jump start
with Voltus adoption -- it was a struggle to create all the
power-grid views correctly. We hope that Voltus R&D puts more
focus on improving flow usability and bulky nature of power-grid
views going forward.
- Although it's nice to have Voltus handle our 200+ M instance
designs hierarchically, we would like to see this same work done
flat in the future. I don't want to have to generate the abstracts
for the blocks in a hierarchical approach; flat just does it.
Compatibility-wise, the new Voltus tool is quite compatible with their old
EPS tcl scripts. We didn't have to spend much time on script redevelopment
or flow-reengineering to adopt the new tool.
We were pleasantly surprised by the 9X boost in runtime we've seen so far
with Voltus. It helped us to hit our tape-out schedule.
- [ A Little Bird ]
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