( ESNUG 535 Item 3 ) -------------------------------------------- [12/20/13]
Subject: User benchmarks BDA AFS Mega vs. Finesim Pro and HSIM for SRAMs
> AFS Mega is a high-capacity (100 M+ elements), fast and accurate SPICE
> simulator for memories. It uses a SPICE engine instead of a digital
> fast SPICE engine like FineSim Pro, so it does NOT make any of the
> approximations -- like table look-up for models or event-driven-based
> simulation. So it's even faster than FineSim Pro, as well as more
> accurate. We looked at it because TSMC said they're supporting it.
>
> BDA's AFS Mega is the first simulator we have seen that can handle the
> extremely dense parasitic netlists that see coming out of extractors
> at 28 nm (and below), which include interconnect parasitics. These
> parasitic coupling capacitances are a significant portion of total
> capacitance! They're a major headache for digital fast SPICE.
>
> - from http://www.deepchip.com/items/dac13-04.html
From: [ Horse With No Name ]
Hi, John,
Please keep me anonymous for fear of retribution.
We use AFS Mega for designing SRAM macros based on 28 nm technology. Here
is a summary of what we did:
- designed 12 different macros from 16 K to 0.5 M.
- have two types of circuits we needed to analyze for
each size: a critical path (a specific cut of a
netlist) and a full macro.
- For each circuit, we needed to run 16 different corner
conditions that vary process and temperature conditions.
We are going to increase this to account for double-
patterning effects as well.
- We ran two types of simulations for each corner.
a. Timing: We needed to run timing simulations with
accuracy within 2-3% of the golden reference,
which is always HSPICE or Finesim SPICE in HD mode.
b. Power: We needed to run power SPICE simulations with
accuracy better than 5%. We did not need this
accuracy for power simulations before, and digital
FastSPICE only gives us accuracy to the level of
20-25% for current measurements anyway (because they
don't simulate currents very well). Now, we need to
characterize properly for power because processor
chips contain so much embedded SRAM and power and
leakage current issues in SRAMs is a big factor.
We ran AFS Mega using its default mode. The results met our requirements.
We also found accuracy of currents to be far better than Cadence XPS or
Synopsys FineSim Pro for memories. The largest macros we simulated were
about 100 million elements for 28nm. BDA says AFS Mega's capacity is
greater than 100 million elements - it had better be because parasitics
will drive our required capacity to 100-120 million elements.
In some cases, our design could not run in a reference SPICE simulator like
HSPICE, so we needed to run our reference simulation in BDA AFS because it
was the only simulator we could run a SPICE-accurate macro simulation in.
---- ---- ---- ---- ---- ---- ----
AFS MEGA EVALUATION
Below are highlights from our eval. FYI, I personally ran most of the
simulations.
1. Runtime
AFS Mega got the same or better runtime vs. Finesim PRO on every SRAM memory
circuit.
- AFS Mega was typically 1.2X to 2+X faster than FineSim PRO.
- Our shortest run in AFS Mega was 32 mins, our longest run
was 11 hours.
- 3 representative benchmarks below
Circuit AFS Mega Wall-time Finesim Pro Wall-time
BM Size for 4 corners (hrs) for 4 corners (hrs)
---- ------- ---------------------- ----------------------
A 16 K 1.8 hrs 2.2 hrs
B 144 K 6.0 hrs 8.9 hrs
C 512 K 11.4 hrs 16.1 hrs
2. Timing Accuracy
AFS Mega met our accuracy requirements.
To assess AFS Mega's accuracy, we compared it to Synopsys HSPICE (when the
result was possible) or otherwise Finesim PRO SPICE in HD mode. AFS Mega
also has a "gold setting". We sometimes used this "gold setting" in the
beginning just to compare it with AFS and HSPICE. In cases where we had a
large macro, it was the best way to compare the error of our measured result
vs. our golden result (because of the capacity of AFS Mega).
Our requirements are pretty simple: 2-3 psec timing error, or 2% accuracy,
and our threshold value to classify a run as an outlier is 2% or 2 psec.
We then measure the outliers as a percentage of total number of runs for
our 28 nm circuits.
The accuracy with AFS Mega's default settings were very good accuracy and
had very few outliers.
Acceptable outliers: 5.0%
Average outliers:
BDA AFS Mega 2.9%
Synopsys FineSim 7.0%
Also, we normally had to tune FineSim Pro for each circuit and sometimes
for each corner. This was extremely time consuming, as the many runs across
many options to find the best settings takes many hours or days.
This is an area where AFS Mega provides a significant advantage since we did
not have to tune across corners and circuit types. For example, for a given
circuit type (e.g. dual-port SRAM of all sizes) we did not have to tune
across corners.
3. Power Accuracy
We had different SPICE simulator settings for timing simulations and power
simulations with AFS Mega, but we did not have to change these for each
corner or for each macro size.
To calculate power, we simulate the post-layout netlists of the full macros
with extracted power nets included. We typically used FineSim Pro to
simulate our circuit and calculate the relevant currents. Current
measurements are essential to power measurements. Current measurements
from a SPICE run must be accurate to get an accurate power estimate.
Our golden power results come from Synopsys HSPICE. If our circuit could
not run in HSPICE, our golden results came from AFS (not AFS Mega). I do
not have specific benchmark data to cite here, but below are our general
findings:
- FineSim Pro - the accuracy of its current measurements is
approximately 20-30%, and no better. This is because of
digital fast SPICE technology approaches to estimating current.
- AFS Mega - consistently provided current accuracy within
3%-6% of golden results.
As mentioned above, we are seeing a requirement from our customers for power
accuracy to be 5% of golden for our SRAMs -- this is because of mobile
applications.
4. We completed characterization of our full suite of 12 different macros in
two days on ten 8-core machines. AFS Mega runs on 8-threads by default.
5. After a three month evaluation using the tool on our project deliverable,
we decided to adopt AFS Mega for our SRAM macro development work.
---- ---- ---- ---- ---- ---- ----
We have a complete infrastructure just for doing memory characterization for
timing analysis and power analysis that is used for critical path and full
macros. This was built around HSIM then modified for FineSim PRO. We have
now adopted it for AFS Mega.
- The changes were minimal. We learned about some changes we need
to make from BDA -- because the accuracy of measures now needs
to be very tight, and we were kind of sloppy in some areas before.
However, because of our higher accuracy requirements for faster
memories and low-power, we had to change some things.
- These did not require any changes to the infrastructure -- just
our measure and processing scripts.
- We are also changing/improving our flow to handle these monster
interconnect parasitic networks.
Also, the BDA applications engineering team for memory is killer. They have
experience in digital fast SPICE and pure SPICE, and understand exactly how
these design netlists are changing. Anyone evaluating AFS Mega will learn a
lot from these guys about how to better characterize SRAM circuits.
- [ Horse With No Name ]
Join
Index
Next->Item
|
|
