( ESNUG 538 Item 14 ) ------------------------------------------- [10/24/14]
Subject: Trent's ICCAD'13 Trip Report 10 days before the upcoming ICCAD'14
> Next week ITC will be held in Seattle. Everyone who is anyone in
> test will be there. And before ITC happens, I want to ...
>
> - Luis Basto, DFT consultant
> http://www.deepchip.com/items/0538-12.html
Hi, John,
I thought it was a clever idea by Luis Basto to write about some test
topics 4 days right before the International Test Conference (ITC).
In that vein, I'd like to share my ICCAD'13 Trip Report with you so
your DeepChip CAD research readers would come to the ICCAD'14 that's
coming up in 10 days.
- Trent McConaghy, CTO
Solido Design Automation Saskatoon, Canada
---- ---- ---- ---- ---- ---- ----
From: [ Trent McConaghy of Solido Design ]
ICCAD 2013 was held Nov 8-12 at the San Jose Hilton, San Jose, CA. ICCAD is
a highly respected academic conference for EDA/CAD researchers. About 420
people attended. There was a healthy dose of papers on analog, memory, and
variation-aware CAD. Here, I describe seven works that caught my attention.
Paper: BAG -- A Designer-Oriented Integrated Framework
for the Development of AMS Circuit Generators
Authors: J. Crossley et al. (UC Berkeley)
The Berkeley Analog Generator (BAG) is founded on the idea that AMS circuit
designers must spend far too much time fiddling with the technology-specific
implementation details of layout and sizings, and not enough time on
exploring the bigger-picture design options.
Usually, this is where researchers say "and then we built an optimizer" ...
and designers promptly ignore it. BAG takes a different approach; it can be
thought of as a collection of extra-powerful, easy-to-codify P-cells.
BAG is "parameterized design procedures that produce sized schematics and
correct layouts", which are technology-independent. They are easy to edit
and read, because they use Python; and in turn they leverage Synopsys' PyCell
framework which has "DRC correct-by-construction" functions.
A design flow with BAG includes viewing the schematic and layout. But a
central part of the flow is editing Python code, with immediate
schematic/layout feedback.
- Code can specify schematic-level information, such as "use fastest
transistor available" and compute width via a lookup table from
designer-set gm/Id values.
- BAG has layout programmability too, such as setting a cell's
polysilicon density, aspect ratio, a metal-on-metal capacitor's
number of metal layers, and DAC resistor string architecture
(e.g. 1 vs. 2 vs. 3 levels of hierarchy).
The authors provide two case studies with BAG: a voltage-controlled
oscillator, and a switched-capacitor DC-DC regulator with three different
layouts for different power density / output levels. As a hint to the
promise of BAG, these example designs have far more devices than circuits
in typical CAD literature.
---- ---- ---- ---- ---- ---- ----
Paper: A New Methodology to Address the Growing Productivity
Gap in Analog Design (Invited)
Authors: David White (Cadence Design Systems)
David White runs Cadence's Virtuoso group, which nicely calibrated his
perspective on improving analog design productivity. David started his
talk by reviewing the status quo three-step flow for analog design:
- schematic entry (20% of designer time)
- first round layout (50% of time)
- extraction / re-simulation / electromigration(EM)-checking /
editing layout (30% of time)
He then described a revised flow called Electrically Aware Design (EAD).
It merges the last two steps into one faster, unified step. This means:
- Have incremental electrical verification with each layout design
decision
- Give visibility into the effect of the changes.
Incremental electrical verification means incremental extraction, fast
parasitic re-simulation, and incremental EM-checking. Fast incremental
extraction is partly enabled by pre-computing capacitances for common
geometries, then in real-time "pattern matching" the layout geometries to
pre-computed values.
Incremental EM-checking is enabled by comparing each wire's pre-layout
simulation results to predicted post-layout results, and making it fast and
convenient to re-size or re-route the wire.
Visibility means having a simultaneous view of both schematic and layout.
A shared database is key, as it maintains connectivity and electrical
information; and doesn't need LVS, which can be error-prone and
computationally costly.
This isn't just a pipe dream. The Cadence Virtuoso team said they have been
working towards this vision over a number of years, and Virtuoso now supports
an EAD flow. Users have found EAD style flows reduce overall design time by
up to 30%.
---- ---- ---- ---- ---- ---- ----
Paper: Analog Behavior in Custom IC Variation-Aware Design (Invited)
Authors: Trent McConaghy (Solido Design Automation)
This work starts off by providing an example of how variation challenges are
growing: in GlobalFoundries process technology, Idsat variation doubled
going from 40nm to 28nm. Device-level variation causes circuit performance
variation, which in turns hurts yield.
As the paper states, "there have been many proposals over the years to
counter the effects of variation. Revolutionary changes to methodology have
been proposed, such as mandating automated sizing or direct MC on response
surface models. Fortunately, there's an easier way; no revolution is
necessary."
The easier way is simply *better corners*, where the corners capture the
bounds of circuit performances, rather than device performances. Each
corner is a point in process variation space, which includes a value for
each local process variable of each device, and for each global process
variable. Designing on x-sigma corners implicitly designs for x-sigma
yield, without needing Monte Carlo in the loop.
The paper illustrated the approach on a 4-sigma flip-flop design, having
about 200 process parameters.
- The first step extracted a 5-sigma corner using the Solido
High-Sigma Monte Carlo (HSMC) tool for high-sigma analysis.
From 100 M MC samples generated, and under 2000 simulations,
it found the Monte Carlo sample with 5-sigma setup time and
set it as the corner.
- The second step used Solido Cell Optimizer to globally auto-
size widths and lengths to minimize setup time, simulating
against the 5-sigma corner.
The final step ran Solido HSMC again, to verify the design. Overall 5-sigma
setup time was reduced by 32%.
---- ---- ---- ---- ---- ---- ----
Paper: Fast Statistical Analysis of Rare Circuit Failure Events via
Scaled-Sigma Sampling for High-Dimensional Variation Space
Authors: Shupeng Sun et al. (Carnegie Mellon University, with
co-authors from CMU and Cadence)
This paper introduces a new approach for high-sigma analysis, called Scaled
Sigma Sampling (SSS).
In the literature, the high-sigma approach of Importance sampling (IS) is
popular, usually on 6-dimensional problems (Vth's on a 6T SRAM bitcell), or
perhaps 12-d (include betas). This paper benchmarks Minimum-Norm Importance
Sampling (MNIS) (Qazi et al, DATE, 2010) as a representative IS algorithm on
high-d problems:
Circuit # var True fail rate MNIS fail rate MNIS error
------------- ----- -------------- ---------------- ----------
Memory Column 384 1e-6 2.2e-10 4500x
[2.7e-11,4.2e-10] [misses 1e-6]
DFF 280 1e-5 1.5e-7 67x
[0,3.4e-7] [misses 1e-5]
To help understand the issue, recall that the IS's central idea is to
distort the sampling distribution, such that more samples fail. Most IS
approaches draw from a normal distribution, shifting the mean towards the
failure region, and sometimes changing the standard deviation (or covariance
matrix) to hug the failure boundary better.
IS errs when the shifted samples are too far past the failure region (weight
is too small to affect yield), when failure regions are missed, or when the
samples don't capture enough of the failure boundary.
In IS, to calculate yield, each sample is weighted, according to the true &
sampling distributions. The paper shows that when yield is calculated this
way, variance of the yield estimate is exponential in the input
dimensionality.
The authors propose SSS, for high-dimension high-sigma.
- For its sampling distribution, SSS does not shift the mean.
Instead, it only enlarges the standard deviation via a nonlinear
scaling factor. This factor is computed from some initial pilot
simulations. This strategy helps it mitigate the traditional IS
sources of error.
- When estimating yield from the samples, it does *not* calculate
yield directly from sample weights. Instead, it employs a more
complex method that fits a model relating yield to the norm of
the closest failing point, and leverages a "soft maximum"
approximation. This helps it mitigate high variance in high
dimensions. While other IS approaches have used model fitting
to estimate yield (T. Hesterberg, PhD thesis, Stanford, 2003),
the approach presented here is promising.
- SSS estimates confidence intervals via the statistical technique
of bootstrapping (B. Efron, Annals of Statistics 7(1), 1979)
The authors tested SSS on the same circuits as before:
Circuit # var True fail rate SSS fail rate SSS error
----------- ----- -------------- --------------- ---------
Memory Column 384 1e-6 0.73e-6 1.36x
[0.019e-6, 5.6e-6] [covers 1e-6]
DFF 280 1e-5 1.6e-5 1.60x
[0.176e-5, 8.9e-5] [covers 1e-5]
In short, SSS greatly reduced the error compared to MNIS, and the error
bounds successfully covered the true value. As far as I could tell, if SSS
had erred badly, there would have been no indication.
---- ---- ---- ---- ---- ---- ----
Paper: Verifying Start-up Failures in Coupled Ring Oscillators in Presence
of Variability using Predictive Global Optimization
Authors: Taehwan Kim et al (Seoul National University, with
co-authors from SNU and Samsung)
This paper aims to verify a coupled ring oscillator across possible initial
circuit states, subject to process variation.
It casts the problem as a global optimization problem. It searches for
maximum (worst-case) settling time. It models possible initial states with
a voltage at each node, where each voltage is from 0 to Vdd. It models
process variations via 1000 Monte Carlo samples, for 99.9% confidence.
The optimizer uses model-building to reduce simulations. It operates as
follows:
1. Draw a set of points that are well-spread in the "input space"
of initial states. Simulate each of those points on 1000 MC
samples.
2. Choose a new point by (a) building a radial basis function (RBF)
model of input space to settling time (b) running an "inner"
optimization that finds a point with the maximum model-predicted
settling time, accounting for uncertainty. Simulate that point.
3. If either a startup failure is found, or confident that no
failures exist, stop. Otherwise, go to (2).
The authors verified the paper's approach on a few variants of coupled ring
oscillators on 45nm CMOS. There were 543,803 possible initial states. The
approach only needed evaluate 11-16 states (11K-16K simulations) to verify
the oscillator, for a speedup of 34,000x.
---- ---- ---- ---- ---- ---- ----
Paper: Scalable and Efficient Analog Parametric Fault Identification
Authors: Mustafa Yelten et al (Intel)
The authors attack a problem in analog test: find as many process
variation-induced failures as possible, with just 200 test samples
(simulations). The baseline / traditional approach runs 1000 Monte
Carlo-based test samples, which is roughly a 3-sigma analysis. Improving
upon the baseline reduces test costs in high-volume manufacturing.
This paper's approach, called Iterative Failure Search (IFS) is to focus
Monte Carlo-style samples on high-impact parameters. The steps of IFS are:
1. Sensitivity analysis: for each process parameter and each +/-
direction, perturb the parameter 3 standard deviations in that
direction and simulate.
2. Draw initial samples, where each low-impact parameter is drawn
from a uniform distribution, and each high-impact parameter has
a fixed value in the failure direction (based on sensitivity).
Simulate samples.
3. Draw adaptive samples, where each sample is the sum of (a) the
previous iteration's sample that is closest to the failure
boundary, and (b) a step of randomized magnitude towards the
failure direction. Simulate samples.
4. Stop if any failures are found, otherwise go to (3)
At first glance, the approach may appear like a high-sigma algorithm.
However, its 1000 Monte Carlo samples baseline means it's for 3-sigma
analysis. (High-sigma analysis is typically 1M to 1G+ samples baseline.)
The approach was demonstrated on two test cases.
The first test case was a signal converter with 498 elements, as part of a
serial IO receiver's phase interpolator. From 188 parameters considered,
sensitivity analysis identified 4 high-impact parameters. In the authors'
case, sensitivity analysis came for free, because it was performed as part
of a previous step in the design flow.
Three separate IFS runs were performed, for three threshold levels of
increasing aggressiveness. For comparison, three Monte Carlo runs were
performed as well. Each run had 200 simulations. The table below show how
many failures each approach found.
Threshold MC # failures IFS # failures
--------- ------------- --------------
u1 17 200
u2 1 87
u3 0 57
We see that IFS always finds far more failures than MC. Furthermore, via a
clustering analysis, the authors also showed that IFS discovered multiple
failure regions.
The second test case had four combined blocks (phase interpolator core,
filter, biasing unit, output buffer), having 1160 circuit elements, as part
of a serial IO receiver. With the same testing methodology:
Threshold MC # failures IFS # failures
--------- ------------- --------------
u1 14 200
u2 0 200
u3 0 83
From 874 parameters considered, sensitivity analysis ID-ed 4 parameters.
---- ---- ---- ---- ---- ---- ----
Paper: From Statistical Model Checking to Statistical Model Inference:
Characterizing the Effect of Process Variations in Analog Circuits
Authors: Yan Zhang et al. (U. Colorado, with co-authors
from U. Colorado and RWTH Aachen)
This paper considers the problem of verifying analog circuits that are
subject to process variation. It computes whether a circuit hits a target
yield for a given circuit specification (e.g. gain > 60).
This paper presents an approach called Statistical Model Inference (SMI).
SMI has the following steps:
1. Build a polynomial regression model mapping process variables to
output. It does this by drawing samples from the distribution,
simulating, and building a new model. It repeats this until the
model parameters stabilize. Cross-validation measures parameter
stability.
2. Compute a +/- confidence interval ("bloat interval") for the
model predictions. It performs this as follows. First, it
initializes the interval to +0 / -0. Then, it draws a sample
and simulates it. If the sample's output value is within the
+/- interval of the model-predicted values, it passes. If not,
it increases the interval size. It repeats this until it passes
K times in a row. K is based on target yield.
3. Use the model and bloat interval to compute yield (or to compute
the safe subset of parameter space). For example: draw 1e6 MC
samples; each sample passes if its model-predicted value + bloat
interval meets the specification; then yield is the % of samples
that pass.
The authors demonstrated SMI on a three-stage ring oscillator (1 output) and
two-stage opamp (9 outputs). The baseline for comparison is 1000 MC
samples.
SMI agrees
Problem #var Step 1 #sim Step 2 #sim with MC
----------------------- ---- ----------- ----------- ----------
ring oscillator freq 6 150 265 YES
opamp input offset vltg 8 240 187 YES
opamp DC gain 8 125 201 YES
opamp UGBW 8 125 111 YES
opamp PM 8 125 117 YES
opamp CMRR 8 125 134 YES
opamp PSRR+ 8 125 119 YES
opamp PSRR- 8 125 98 YES
opamp SR+ 8 250 112 YES
opamp SR- 8 250 139 YES
Simulation time was dominant. The authors note that the number of sims is
highly dependent on the number of parameters.
---- ---- ---- ---- ---- ---- ----
Paper: Bayesian Model Fusion: A Statistical Framework for Efficient
Pre-Silicon Validation and Post-Silicon Tuning of Complex
Analog and Mixed-Signal Circuits (Invited)
Authors: Xin Li et al. (Carnegie Mellon University, with
co-authors from CMU and Intel)
This paper presents a detailed overview of Bayesian Model Fusion (BMF), a
technique that can help in verifying analog circuits under process
variation. BMF has two pillars:
1. Given an a priori model (an existing understanding of the world),
and new data, we can use Bayes' rule to update the model.
2. Create the a priori model from many *cheap* measurements (e.g.
pre-layout simulations); so that we can minimize the number of
*expensive* samples of new data (e.g. post-layout simulations,
or test measures).
Thus, the BMF approach is quite general, and mathematically very clean. The
authors envisioned many applications. They give results for three:
- Estimating mean, standard deviation, and higher-order moments.
For a high-speed I/O link's, to estimate the time margin output's
mean in post-silicon within 2% error, BMF used 5 samples, versus
11 without BMF.
- Estimating density; from which mean, stddev, yield, etc. can be
computed. For an SRAM read path in 32nm, to estimate the delay
density within 2% error, BMF used 10 post-layout simulations,
versus 100 without BMF.
- Estimating parameters for a regression model of process variables
to output, with application to post-silicon tuning. For a VCO in
32nm, BMF needed 2 measured chips to determine an accurate tuning
policy, versus 6 without.
---- ---- ---- ---- ---- ---- ----
Again, if any of your EDA/CAD researcher readers are thinking of coming to
the ICCAD'14 in 10 days, tell them they should sign up soon!
- Trent McConaghy, CTO
Solido Design Automation Saskatoon, Canada
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