( ESNUG 540 Item 7 ) -------------------------------------------- [05/16/14]

Subject: Hogan on SNPS, CDNS, Atrenta, CLKDA, Solido as low voltage tools

From: [ Jim Hogan of Vista Ventures LLC ]

Hi, John,

Below are the major EDA vendors who have currently added significant
"low voltage" design aspects to their tools.

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LOW VOLTAGE RTL-LEVEL PLAYERS

Low voltage RTL-level design uses a mix of power planning, power estimation,
power reduction, restructuring, power verification, and IP.

I cite only the key general players here -- and I'm purposefully ignoring
those who only offer one thing in one category  (e.g. Calypto only does RTL
power reduction or only ARM for IP).

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LOW VOLTAGE BLOCK/CELL-LEVEL PLAYERS

Here designers use a mix of characterization and transistor-level timing
tools to capture variance and complex delay effects.  

Cadence Virtuoso Liberate and Variety.   Virtuoso Liberate is a cell, memory
and block characterization tool used primarily to create CCS and ECSM delay
and noise models for std cells.  Virtuoso Variety is basic variance modeling
to generate single load slew point AOCV tables, as well as SOCV tables.  

CLK Design Automation Variance FX.  Variance FX is full variance analysis
tool used to generate AOCV, POCV, and full arc/load/slew Liberty Variance
Format tables, as well as constraint uncertainty.  Voltage FX adds voltage
and process analysis to evaluate cell and library performance at extreme
voltage conditions.

CLK Design Automation Path FX and Clocktree FX.  Path FX is a transistor
level static timing analysis tool that works with PrimeTime to evaluate
critical paths for SPICE accurate delay and variance.  Clocktree FX
complements Path FX with similar capability for all of the clock trees in an
SoC.  

Synopsys Magma SiliconSmart.  SiliconSmart is a general-purpose cell
characterization tool used primarily to create CCS delay and noise models
for standard cells.  It has basic variance modeling capability to generate
single load slew point POCV and AOCV tables.

Synopsys NanoTime.  NanoTime is a transistor level timing system used to
model custom blocks and memories.  It combines static timing and SPICE to
validate the blocks, and to generate black box models for use with
PrimeTime.

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LOW VOLTAGE TRANSISTOR-LEVEL PLAYERS

Here designers use a combination of variation and SPICE simulation tools.
Players in these areas include:

Agilent GoldenGate.   Agilent's SPICE is mostly used by RF engineers for
design and verification of RF blocks both at legacy and advanced process
nodes.

Cadence Spectre/SpectreRF.   These transistor-level SPICE simulation and
verification tools are used by analog/RF and custom digital designers.  

Mentor Eldo/BDA AFS.   Eldo SPICE does transistor-level verification for
analog/RF and custom digital design -- mostly for legacy process nodes.
MENT's recent acquisition of Berkeley Design Automation gives them the
BDA AFS simulator; which will open up advanced nodes for analog/RF, full
custom digital and memory design for them.

Silvaco SmartSpice.   Silvaco's SPICE is primarily used for analog/RF
design and verification at the transistor-level.

Solido Variation Designer.   Solido improves power, performance, area and
yield by eliminating over-design and under-design caused by PVT and 3- to
6-sigma Monte Carlo variation.   Their software is used for memory, std
cell, custom digital and analog/RF design at the transistor-level.

Synopsys HSPICE/CustomSim/FineSim.   The 9 Synopsys SPICE simulators are
primarily used for transistor-level design and verification for memory
and standard cell designs.

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Lower energy is a multi-dimensional chip design problem.  The landscape will
change quickly.  If anyone has any new updates or insights on it, please add
them to this discussion.

    - Jim Hogan
      Vista Ventures                             Los Gatos, CA

 Editor's Note: Jim Hogan is on the boards of both CLKDA and Solido
                plus is a technical advisor to Atrenta.  - John

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    Hogan on SNPS, CDNS, Atrenta, CLKDA, Solido as low voltage tools

   !!!     "It's not a BUG,
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