( ESNUG 545 Item 3 ) -------------------------------------------- [11/20/14]
From: [ Cliff Cummings of Sunburst Design ]
Subject: Cliff needs your help finding a SV-to-SystemC synthesis professor
Hi, John -
In the mid-1980s, a new type of tool emerged called the silicon compiler.
Many companies created such tools with proprietary input languages, but
one company, Synopsys, noted that engineers seemed to really like this
up-and-coming simulation language from Cadence called "Verilog".
Aart told engineers that if they would code their designs in a subset of
Verilog that his Design Compiler would synthesize their Verilog designs
into hardware.
We now refer to that subset as the RTL Synthesis Subset of Verilog.
Fast-forward to today. Engineers really like the enhanced System Verilog
language -- but would still like to have the speed of SystemC at the chip
architectural level.
Many engineers, myself included, strongly dislike the SystemC syntax but
understand that the cumbersome syntax is required to compile designs in
C++ for high speed simulation.
For years I have tried to convince EDA companies to define a System Verilog
subset that could be converted into high-speed SystemC designs without the
need to code in SystemC.
I would like to find the SystemC Simulation Subset of System Verilog.
The advantage of this approach is engineers could code in their preferred
System Verilog language -- that could still be simulated in a System Verilog
environment -- while allowing that exact same design to be converted into a
high-speed SystemC model.
Many companies have shown interest in this idea but none have followed
through to create such a tool. I finally realized that nobody was building
the tool because it is basically a high-speed translator so each potential
client might only need one license to build the SystemC models. There isn't
enough profit in building, selling and supporting such one-license tool.
I might like to build this tool and possibly make it publically available,
but I need some help from your DeepChip readers.
To make this project worthwhile, I'd like to pursue this as Ph.D. project at
a top-ten computer engineering graduate school. I don't really need a Ph.D.,
but if I do pursue a Ph.D., I would like to find a professor that is doing
research in this area and work with him/her on this project.
I found the U.S. News list of Top 10 Computer Engineering Graduate Schools:
#1 Massachusetts Institute of Technology Cambridge, MA
#2 Stanford University Stanford, CA
#3 University of California Berkeley Berkeley, CA
#4 Carnegie Mellon University Pittsburgh, PA
#5 University of Illinois Urbana-Champaign Urbana, IL
#6 University of Michigan Ann Arbor Ann Arbor, MI
#7 Georgia Institute of Technology Atlanta, GA
#8 Cornell University Ithaca, NY
#9 Purdue University West Lafayette West Lafayette, IN
#10 University of Texas Austin Austin, TX
If any of your army of DeepChip readers knows of any professors at these
universities who are working in SystemC/SV/symthesis, could you have them
either contact me at cliffc@sunburst-design.com or to please pass my phone
number (801) 960-1996 to their computer engineering departments to see if
any professor there is interested in mentoring this research topic?
This is a possibly interesting twist on SystemC design creation.
- Cliff Cummings
Sunburst Design Provo, UT
Editor's Note: Wow. Cliff Cummings applying to do System Verilog
to SystemC research is like Isaac Newton applying to do physics.
Cliff personally defined 90% of the SV standard! Wow. - John
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Related Articles
Cliff's SNUG'00 1st Place Paper on Nonblocking Verilog Assignments
Cliff speaks for System Verilog; Shalom and others for Specman "e"
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