( ESNUG 546 Item 2 ) -------------------------------------------- [01/15/15]
Subject: User seeks Incisive/Questa/VCS/Aldec benchmark for Verilog/VHDL
> 2.) What are the biggest EDA/FPGA/FAB/IP headaches that your design
> or verification team is dealing with today?
>
> - from http://www.deepchip.com/wiretap/150108.html
From: [ The Birdman ]
Hi, John,
I am looking for recent discussions and/or benchmarks of how these RTL
simulators compare:
Cadence Incisive
Mentor Questa
Synopsys VCS
Aldec Riviera Pro
Our design is largely VHDL, but mixed-mode is required for Verilog IP.
Need the simulator for both ASICs and FPGAs. What are their relative
speeds? Ease-of-use? Relative costs? Compatibilty issues?
Please don't share this email address with anyone and keep me anonymous.
- [ The Birdman ]
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