( ESNUG 547 Item 3 ) -------------------------------------------- [02/06/15]
Subject: 16 nm FinFET memory designer on Spectre-XPS, HSPICE, and Solido
> The Cadence rep claims Spectre XPS is 3X faster than HSIM and it silicon
> correlates better than Synopsys because XPS supposedly has better newer
> convergence algorithms. The rep also claims Spectre XPS is 100% Spectre
> compatible -- no netlist edits (like no tweaks of .MEASURE needed)
> nor special syntaxes needed.
>
> - [ An American Werewolf in London ]
> http://www.deepchip.com/items/0546-05.html
From: [ Swamp Thing ]
Hi, John,
I must be kept completely anonymous, thank you.
We use Cadence Spectre-XPS and Synopsys HSPICE with Solido on our memory
designs. At 28 nm we used to do thousands of Monte Carlo simulations to
3.5 sigma, then extrapolated the results to get to 5.6 sigma.
MONTE CARLO vs. SOLIDO HSMC:
Since going below 28 nm has even more nonlinearities, we had to dump MC and
use Solido High Sigma Monte Carlo (HSMC) instead.
The other thing we liked about this change was the much faster runtimes.
Standard Monte Carlo HSPICE runs vs. Solido HSMC HSPICE runs got:
Runtime
---------
Monte Carlo simulations ~6 weeks
Solido HSMC simulations 2 hours
This was at 16 nm doing 3.5 sigma. That's 120X; it gets to 200,000X when
we got to 5.6 sigma -- saving us man-years of engineering time.
HSPICE vs. SPECTRE-XPS:
Our company had been using Synopsys HSPICE (with Solido.) However, after
doing some benchmarking between Synopsys HSPICE and Cadence Spectre-XPS,
we got 3-4X faster throughput with Spectre-XPS -- and with similar HSPICE
accuracy. Add Solido and throughput speeds up even more.
A representative benchmark:
Design size: 200 FinFETs 16 nm
Spec: 700-1,000 picosec
Synopsys HSPICE: 2 min
Cadence Spectre-XPS: 35-40 sec
So technically we switched from Solido/HSPICE to Solido/Spectre-XPS. To do
this we needed to alter our Solido flow a bit:
- With HSPICE, we could put the .MEASURE statements in our SPICE deck.
- With Spectre-XPS, first we had to figure out the new flow, which took
some effort. After that, it was easy to implement: we did some SPICE
post-processing to measure the parameters we wanted, and then we fed
it into the Solido HSMC optimizing algorithm.
Here's where we compared standard Monte Carlo vs. Solido HSMC:
Design: 5.6 sigma requirement, 200 FET design in TSMC 16FF+
Base run: 40 sec in Spectre-XPS
# of simulations Total Time (calculated)
---------------- -----------------------
Standard Monte Carlo 1.7 Billion 2,156 years
Solido HSMC 8,000 3.7 days
The number of simulations with Solido depended on the specific circuit and
the number of FETs; the more FETs, more simulations that were required.
Solido's range was 4,000-12,000 simulations.
METHODOLOGY AND RESULTS:
We've used Solido HSMC for two memory designs: 5.6 sigma and 5.8 sigma.
As an example, here are our steps we used on a match line sense amp in a
5.6 sigma TCAM (Ternary Content Addressable Memory) design:
1. We ran Solido HSMC with Spectre-XPS. It showed that our design
did not meet performance spec due to variation problems.
2. When the circuit failed, Solido saved off the circuit with the
FET parameters, so we could see how to reproduce those failures,
and how things were skewed. We could see how the FETs were
modified in the SPICE deck with 5.5+ sigma variation.
3. We were balancing between catching a "0" and catching a "1" in the
circuit. i.e. if we were failing on catching a "0", but not a "1",
then we would modify the appropriate transistors and directions
to better balance the operation of the circuit.
4. Our sense amp has ~20 transistors. We understood our circuit well
enough to modify 3 FET transistor sizes.
5. We then reran the Solido HSMC with Spectre-XPS on the circuit.
Most of the simulations that Solido HSMC runs are at the tail of the
distribution curve, close to the sigma limit. Solido showed about 1,000
failures out of 10,000 Solido runs, which is equivalent to 1000 failures
in 1.7 Billion equivalent simulations.
We liked that Solido could do Spectre-XPS and HSPICE runs in parallel. We
ran ours on 100 nodes. It's not quite linear, maybe 50% linear. That is,
going from 25 nodes to 75 nodes would cut the runtime in half; not 1/3rd.
---- ---- ---- ---- ---- ---- ----
Overall, Solido gave us a 5X reduction in our compute resources -- we used
only 20% of our prior HW and 20% of our Spectre-XPS and HSPICE licenses.
Spectre XPS gave us 3X to 4X speed up over HSPICE, with HSPICE accuracy.
Solido HSMC also allowed us to reduce our design risk. And because we did
more thorough variation analysis, we could actually design closer to the
edge, as we didn't have to add as much margin for the unknown as we did
for our prior memory designs.
- [ Swamp Thing ]
---- ---- ---- ---- ---- ---- ----
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