( ESNUG 547 Item 8 ) -------------------------------------------- [03/09/15]

Subject: Big A/Little D user on SNPS Custom Designer vs. CDNS Virtuoso

>  You wrote that Custom Designer failed in 2010.  That was 5 years ago.
>  Is that still true now?  We can't find any Custom Designer users
>  except for some Synopsys press releases on the Synopsys web site.
>
>  Do you have any independent user assessments of Custom Designer?
>  Is anyone big using it for production full custom design?
>
>      - from http://www.deepchip.com/items/0546-04.html


From: [ All Hail Megatron! ]

Hi, John,

Could you keep me anonymous please?

Somebody asked you if anybody used the Custom Designer flow.  Well I used it
for the first time in 2011 when I was working as an independent contractor
for an IC company to do xtal-oscillator design-and-layout in TSMC 28 nm.

Custom Designer was not that bad.


OUR CUSTOM IC'S

We used it a real small block, maybe around 100 transistors.  The difficulty
was that that block had to be really low power, around 2 uA nominal current
consumption -- which meant almost all the transistors had to work in their
subthreshold region of operation.  (Such designs require the designer to
know how to setup their SPICE simulator options to make sure the results are
reliable for very low currents.)  We had a similar case for a UHF RFID chip
we designed.  Whole chip used supply current levels as low as 9 uA.

Our designs are normally Big A/Little D.  In the RFID chip we designed here,
the chip area was around 0.8mm x 0.8mm.  Thus, it is really small chip.  Our
digital block was a state machine and had around 3,500 gates.

In fact I enjoyed Custom Designer better than Cadence Virtuoso as it was
less confusing in my opinion.  Our chip worked at the first tape-out.


OUR SNPS CUSTOM FLOW

Since then we licensed the whole SNPS Custom Designer flow for the design
group I am managing here.  My group is not large, around 4-5 designers.
We also use ClioSoft SOS to manage our design data.  I also manage both CAD
setups and PDKs.  We used both full analog (with Synopsys HSPICE/RF) as well
as the SNPS mixed-signal simulation flow (CustomSim-VCS).  Star-RCXT for
extraction.

HSPICE-RF has actually become quite a decent SPICE simulator.  Maybe not as
robust as Spectre-RF or Eldo-RF, but very usable.  However the HSPICE-RF
documentation is horrible.  It was written by the software engineers for
the software engineers.  Could you believe that there is not a single app
note written for HSPICE-RF???

I am afraid we don't do much scripting.  Synopsys uses TCL.  Like Virtuoso
ADE's Ocean scripts, Custom Designer SAE can create TCL scripts to run the
SPICE simulations.

Our first chip we taped out works so the results speak for themselves.


LIBRARY AND LEGACY PROBLEMS

The Achilles' heel for Custom Designer is the iPDK availability and the
frequent version changes needed in PyCell setup.  One iPDK requires one
PyCell version, while the the next version would require another PyCell
version with its own bugs.

What we ran into was that iPDKs need a certain Python version and a certain
gcc compiler version.  Synopsys supplied us iPDK from TSMC 130 nm MS/RF
last year.  Once we started the layout in earnest, we found that MIMCAPs
used M7 while our chosen process flavour was only 6 metals.

After some internal struggle, Synopsys supplied us a new version of iPDK,
but this would not work with Hercules DRC/LVS as some "libstdc++" version
was conflicting.  Synopsys is now supplying PyCells with Custom Designer
while it used to be a separate download until the last year.

We really don't have any legacy designs.  This is a new design group who
started with the Custom Designer.  However I was able to move OA databases
between Cadence and Synopsys without problems a couple years back.


SNPS VS. CDNS PRICING

I checked my report at that time for the quotes we got from the different
CAD vendors.  The Cadence quotation was $200 K for two years.  It was:

        - 3 schematic editors,
        - 2 ADE,
        - 2 layouts,
        - 2 Spectre (no Spectre-RF),
        - 1 Assura DRC, and
        - 1 Assura LVS.

Cadence offered no flexibility in licensing terms and if I had a fourth
designer, which we eventually had, there would be no license for him/her.
       
Synopsys had a much more flexible licensing terms with e-licensing option.
The Cadence schematic editor was 2X the price of the Synopsys schematic
editor.  For Spectre vs. HSPICE, the price differential was three times.
Assura DRC/LVS was priced separately -- you could get SNPS ICV/Hercules
for about the same price of one Assura license.  Moreover we could access
a whole menu of both analog and digital tools with our Synopsys flow.


GOOD FOR SMALL START-UPS

I would say the Custom Designer is a work in progress, but it is progressing
rapidly.  Synopsys is putting quite a bit of effort in improving both the
Custom Designer flow and its SPICE simulators.

At the end of the day, performance/price ratio you get with Custom Designer
(so far) has been mostly higher than the Cadence Virtuoso tools.

In summary, Custom Designer should be on the top of the list for the small
design groups who need lower licensing costs than a Virtuoso flow.

    - [ All Hail Megatron! ]

           ----    ----    ----    ----    ----    ----   ----

Related Articles:

    User asks on Pyxis, SNPS Custom Designer, alternatives to Virtuoso
    16 nm FinFET memory designer on Spectre-XPS, HSPICE, and Solido

Join    Index    Next->Item






   
 Sign up for the DeepChip newsletter.
Email
 Read what EDA tool users really think.





Feedback About Wiretaps ESNUGs SIGN UP! Downloads Trip Reports Advertise

"Relax. This is a discussion. Anything said here is just one engineer's opinion. Email in your dissenting letter and it'll be published, too."
This Web Site Is Modified Every 2-3 Days
Copyright 1991-2024 John Cooley.  All Rights Reserved.
| Contact John Cooley | Webmaster | Legal | Feedback Form |

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)