( ESNUG 549 Item 1 ) -------------------------------------------- [04/23/15]
Subject: Hogan follows up on emulation user replies plus market share data
> 5. Speed Range
>
> Emulator speed is measured in cycles-per-second. Processor-based
> speeds range from 100 K to 4 M cycles/sec, while FPGA-based range
> from 500 K to 50 M cycles/sec, depending on the number of devices.
>
> - http://www.deepchip.com/items/0522-03.html
From: [ Jim Hogan of Vista Ventures LLC ]
Hi, John,
I was pleasantly surprised by the 37 users who had commented on my overall
analysis of the emulation/prototyping space from 2 years ago. But I feel
I should have answered some of the issues that they brought up. Would it
be OK to do this now?
>
> Hogan??? Emulation???
>
> ---- ---- ---- ---- ---- ---- ----
>
> Wow. I didn't know Jim knew so much about emulation. I guess
> he gets around.
>
> ---- ---- ---- ---- ---- ---- ----
>
> One of my full custom guys forwarded me this. They didn't know
> Hogan did digital RTL.
>
> ---- ---- ---- ---- ---- ---- ----
>
> WTF? Hogan? Emulation?
>
> - http://www.deepchip.com/items/0530-01.html
I started out playing college football. Back then life was about parties,
memorizing plays, and endless practices. I had no idea back then that I
would be doing anything involved with technology -- much less chip design.
The one big lesson life has taught me over the years is the importance of
constantly reinventing yourself.
So, yes, Hogan, emulation.
>
> The three points we got burned on were:
>
> - Partitioning
> - Compile times
> - Visibility
>
> I can't commend Jim enough for how well he discussed these and the
> pitfalls one can fall into in each of these three areas.
>
> Neither the EVE salesman (for the FPGA side) nor the Palladium
> salesman (for the custom processor side) gave us any warning that
> these three things would be our biggest headaches.
>
> ---- ---- ---- ---- ---- ---- ----
>
> Watch out. When an emulator sales guys says his partitioning is
> automated, he's only making that claim very losely.
>
> And don't get me started about FPGA memory mapping limits.
>
> ---- ---- ---- ---- ---- ---- ----
>
> Loved all the comparative numbers for price, capacity, speed,
> compile times, memory, # of users, etc. This isn't easy to find.
>
> Does Jim have any comparative data of gates/hour for the automated
> partitioning times of Palladium vs. Veloce vs. EVE?
>
> - http://www.deepchip.com/items/0530-01.html
I don't think you can fault an EVE/Palladium/Veloce salesman for downplaying
the headache of partitioning. Partitioning a massive 500 M instance SoC into
2,000 smaller (emulatable) parts is next to impossible for a human engineer
to do. The emulation vendors all now have SW that *helps* do this, but I
agree it still needs a lot of human engineering guidance.
The upside is that this messy chore is doable even for large chips and that,
once done, you generally don't have to repartition again.
Concerning comparative gates/hour partitioning data -- I've not seen that
metric anywhere.
> Hogan should have written more on transactors. They're the life's
> blood of a full emulation-based verification system. Get just a few
> cheap or poorly written TLM's thrown in the mix and you'll be chasing
> your tail for months trying to fix it. Not to mention your throughput
> will be in the toilet.
>
> Also, 3rd party TLM vendors are experts at blaming the other guy's
> TLM for not fully complying to the standard.
>
> ---- ---- ---- ---- ---- ---- ----
>
> I can confirm that it can takes 6+ month to set-up an emulator.
>
> I can also confirm transactors are never plug-and-play. Their care and
> feeding will devour 90% of your time after initial set-up is done.
>
> - http://www.deepchip.com/items/0530-01.html
Yes, add a few poorly written transactors into your project and instead of
verifying your SoC, you'll be devoting your engineering time to debugging
the transactor. There is no such thing as an "inexpensive" TLM. Either
you pay upfront for good quality transactors; or you'll pay later in
engineering man-hours fixing it.
Some have told me that the fear of getting bad 3rd party TLMs is why they
only buy TLMs from one of the EDA Big 3 or from ARM.
With regards to 6 month emulator set-up time; the vendors agree it's a
problem and they're trying to come up with clever ways to cut that.
> SW simulation has not really hit a wall. There's a lot you can do with
> GP-GPUs that nobody is doing yet, and there is also a lot you could do
> with FPGAs if the FPGA compiler flows were more software-centric.
>
> ---- ---- ---- ---- ---- ---- ----
>
> Hogan might want to look at Rocketick. They're doing doing some clever
> stuff with Nvidia GPUs.
>
> ---- ---- ---- ---- ---- ---- ----
>
> I'd love to hear Jim's thoughts about RocketSim.
>
> - http://www.deepchip.com/items/0530-01.html
Yes, I remember there was quite a bit of buzz 2 years ago about using GPUs
for emulation-like tasks. That's when we first heard about Rocketick.
This approach has been used by a few companies, and generally there have
been issues building a generalized GPU product for both RTL and gate level.
As I understand it, Rocketick made a GPU-based accelerator that does the
generalized case. Their production version has gate-level capability.
And I think they just delivered an RTL production version, too.
> The only thing that Jim seemed to gloss over was the prohibitive
> costs to owning an emulator.
>
> Using Hogan's own 2-5 cents per gate data, a Palladium or Veloce
> box for one 200 M gate SoC will cost $4 M to $7.5 M !!! Even a
> Synopsys EVE 0.5-2.0 cents per gate box will cost $1 M to $4 M.
>
> Add service charges and these prices can double.
>
> These costs have to come down for my management to take emulation
> seriously.
>
> - http://www.deepchip.com/items/0530-01.html
I agree. Owning an emulator is expensive; until you figure out the cost of
not owning an emulator. If you try to verify anything over 50 M instances,
you'd have to buy so many SW simulators -- plus the compute farm to run all
these SW simulators -- you've effectively already bought 2 or 3 emulators.
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EMULATION MARKET SIZE AND TOTAL WORLD CAPACITY UPDATE
Market Size
The emulation market grew from $128 M in 2003 to a total of about $390 M in
2013, as derived from EDAC data. This $390 million includes both emulation
(Cadence Palladium, Mentor Veloce and Synopsys Zebu) along with FPGA-based
prototyping (Synopsys HAPS and Cadence Protium). Not all companies are
reporting to EDAC on the FPGA side, but this is probably the right ballpark.
This emulation revenue is derived from EDAC and analysts. My estimates for
FPGA-based prototyping have been subtracted in my chart above. I think
however the numbers above are reliable.
The total world emulation capacity numbers is new emulation capacity sold
in that year. For example, in 2013 enough new emulators were sold that year
to emulate a grand total of 15 billion additional new gates worldwide. (It
looks like annual sold emulation capacity roughly tracks with Moore's Law
over the last couple of years; when it almost doubled every two years.)
In my own personal estimate, emulation/protyping probably now sits at around
$400-450 million as of 2014 -- with strong growth CAGR in the mid-teens.
This makes emulation an EDA growth area and thus very competitive.
- Jim Hogan
Vista Ventures, LLC Los Gatos, CA
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Hogan warns Lauro missed emulation's TOTAL power use footprint
Hogan cautions Frank missed the segway in 2 emulation use modes
Hogan proposes Continuum Of Verification Engines (COVE) concept
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