( ESNUG 550 Item 3 ) -------------------------------------------- [05/05/15]
From: [ Mark Milligan of Calypto ]
Subject: 446 ASIC chip design engineers surveyed on RTL power reduction
Hi, John,
I would like to share with your readers our 3rd annual RTL power reduction
survey. The survey was blind and anonymous. Our prior power surveys were
ESNUG 523 #5 and ESNUG 498 #4.
This survey focused on 446 respondents who were primarily involved with
ASIC design (out of the 750 total survey participants). One of the reasons
for using ASICs instead of FPGAs is lower power -- so many of the power
reduction techniques we were researching are usually only found on ASICs.
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RTL VS. SYSTEM VS. LAYOUT POWER REDUCTION
Question 1: "Where do you most want new tools/features
for POWER REDUCTION?"
Cutting power at RTL was the sweet spot. Almost half (48%) want more power
reduction features there. From the user comments, the design engineers saw
that cutting power at the RTL was their best choice.
With more projects being based around FinFET designs, their focus was more
on dynamic power reduction -- in addition to static power reduction.
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DESIGN TIME VS. ANALYSIS TIME
From our old 2013 survey, we found power analysis took ~30% of the total
low power RTL design time. The rest (~70%) was spent on low power design
decisions.
2013 Time spent on RTL low power design
In rough terms, 2X of RTL low power design was not spent in analysis, but
instead in either guided or automated low power tools themselves.
Guided power reduction is primarily used by RTL designers looking for advice
on where the wasted power is in their design before they freeze their RTL
code. This is where most of power tradeoffs happen.
Automated power reduction is often used by a power team, who typically
receive RTL from the design team (either as new project or pre-existing IP).
The power team applies simulation patterns to measure power, creates new
RTL, and then uses formal to verify their new RTL is functionally equivalent
to the original.
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GROUPS USING RTL POWER TOOLS
Question 2: "What are your organization's plans for
RTL POWER reduction tools for 2014?"
A total of 366 out of 446 engineers answered. As you can see, 39 percent
said their organizations had implemented RTL power reduction tools for 2014.
This was an 18 percent growth. Further, another 44 percent planned to start
evaluation or implementation. A combined total of
83% = 39% implemented + 44% planned
see RTL power reduction was important.
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FAVORITE RTL POWER REDUCTION TECHNIQUES
Question 3: "What are your 3 RTL design techniques
used most often to REDUCE POWER?"
Let's look first at the techniques used *least* often -- and why.
memory vs register file, FSM re-encoding, memory caching,
memory banking, register sharing, register file architecture,
and register cloning
I've highlighted in purple these underutilized areas. Power reductions
from these methods can be big -- yet only 2% to 11% used them.
I believe it's because these methods are hard to do by anyone other than
the engineer coding the RTL (unlike techniques such as clock-gating):
- Many are "microarchitecture" tweaks that involve finding all
the alternatives to determine which is best solution.
- Tricks that worked in one node (28nm planar) may not work in
the next node (16nm FinFET).
- It takes lots of different tool runs -- RTL synthesis, simulation,
guided power & power analysis -- to check these alternatives out.
I expect to see these "difficult" techniques to be deployed more often, and
the result will be less power left on the table.
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CLOCK-GATING STILL RULES
As you can see, 69% said they do RTL clock-gating power reduction.
Clock-gating gets you a lot of bang for the buck by shutting off parts of
the design that aren't needed. It's easy to make these changes by either
the design or power team, because RTL changes have minimal impact on
design functionality.
And half (46%) say they do block-level clock-gating; clearly the leading
microarchecture technique.
But from Question 2 above, only 39% of engineers have tools. Which means
the remaining 30% must be doing RTL clock-gating by hand.
We feel the next step is to reduce RTL power based on going across many
clock states with sequential analysis -- not something doable by hand.
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MEMORY GATING
Only 17 percent did memory gating. This is also hard to do manually.
Embedded memories now have various sleep modes, but to take full advantage
of them requires creating controllers to generate appropriate signals.
Sequential analysis will know when the memory can use those modes and when
it needs to be wakened in time for data to be valid -- as well as when sleep
is greater than power dissipation from going "in" and "out" of sleep.
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FINFETS!
Everyone going FinFETs makes dynamic power critical to RTL low power design.
This plus the other findings in this survey told us:
- Calypto PowerPro will do well with its RTL power analysis,
guided & auto optimization and sequential analysis.
- SLEC Pro will continue to be favored by design teams who must do
formal verification of their RTL changes.
- And our Catapult LP C-to-RTL low power synthesis will do well.
We are seeing a range of power improvement from 5% to 50% from a combination
of either guided and/or automated power reduction modes.
- Mark Milligan
Calypto Design Systems San Jose, CA
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Related Articles:
648 engineers surveyed on RTL Power Reduction and HLS techniques
A wordwide survey of 744 engineers on RTL Power Optimization
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