( ESNUG 551 Item 4 ) -------------------------------------------- [06/26/15]
Subject: Cliff Cummings verification-SystemVerilog-UVM DAC'15 Trip Report
> Cadence Indago is Lip-bu's answer to Aart's Verdi3 empire. Indago
> debug works by adding Big Data Capture to Root Cause Analysis -- in
> order to data mine your CDNS tool run logs -- to "highlight causality"
> and correlations causing your bug in the first place. Indago's big
> idea is to data mine in order to do fewer simulation reiterations.
> (booth 3515) Ask Adam Sherer or Larry Melling. Freebie: Denali tix
>
> - from http://www.deepchip.com/gadfly/gad060515.html
From: [ Cliff Cummings of Sunburst Design ]
Hi, John,
Although I didn't get to see this new Cadence Indago Big Data tool (which
you were so excited about), I do want to share with you some of the other
verification stuff I did see on the DAC Exhibit Floor this year.
Verification Academy
This was my favorite spot at DAC and has been for years. Mentor pulls in
some good presenters to do informative presentations at the booth.
My favorite presentations were by Harry Foster, Mentor Chief Scientist
Verification, on the 2014 Wilson Study commissioned by Mentor. Of note
was that in 2015,
- Verilog would overtake VHDL as the language used to do FPGA
design, with System Verilog coming up fast.
- Among FPGA verification languages, VHDL continues to drop
while System Verilog continues to increase -- with VHDL
still holding a slight advantage as of 2015.
- The only FPGA testbench methodology that is growing is UVM,
with adoption to approach 50% in 2015.
None of these trends surprise me but it was good to see real numbers from
the 2014 Wilson Study.
Full Disclosure: I was also invited to teach one session in the VA booth
on UVM Messaging at this DAC.
---- ---- ---- ---- ---- ---- ----
Starnet FastX - VNC replacement
With some surprise what caught my eye the most for tools at this DAC was the
Starnet Communications tool, FastX, a PC X server that displays EDA tools in
the web browser much faster than a VNC connection.
Of course VNC is free, but VNC tools have to be installed at both ends to
make communication work. This new FastX tool is licensed on the server so
anyone who connects does not have to install any tools on their machine.
This is critical for people like me who want to conduct a remote training
with a fast connection into the GUI on my training server -- but don't want
to require my students to install any software on their computer (which
often requires intervention from the student's IT group).
FastX is pretty cool tool for anyone that needs a fast VNC-like connection
to a server over the web.
---- ---- ---- ---- ---- ---- ----
Rocketick RocketSim
I see you ranked RocketSim as your #1 "to see" in the RTL SIMULATORS section
of your DAC'15 Cheesy Must See List, John.
> Rocketick RocketSim parallelizes your Verilog simulation into multi-
> threads on 100's of regular multicore XEON Servers. Runs 23X faster
> than CDNS Incisive, SNPS VCS, MENT Questa. Does both gate and RTL
> sims. Compiles 1B gates in 2 hours. 4-state-logic for X. Now does
> full System Verilog and accelerates SVAs. Intel, Nvidia investors.
> (booth 3102) Ask Uri Tal. Freebie: backpacks
>
> - from http://www.deepchip.com/gadfly/gad060515.html
I strongly agree with that choice!
RocketSim is basically a fast co-processor Verilog/SystemVerilog simulation
engine. I first took note of RocketSim when they were using Nvidia GPUs as
their simulation co-processor, but at DAC, they claimed to be getting much
faster speedups by using XEON CPU server cores for simulation.
RocketSim is supposed to accelerate Verilog simulations by up to 10X and
reduce memory usage by up to 5X. I believe their current shortcoming is
that they don't run SDF, but they are working on it. I've heard that Intel
Capital and Nvidia are both VC funders of Rocketick. It is certainly a
tool worth watching going forward.
---- ---- ---- ---- ---- ---- ----
Agnisys IDesignSpec
I have watched this company for the past two years. Agnisys has a product
called IDesignSpec that helps generate UVM testbench code and in particular,
it seems to have a nice frontend for generating UVM Register code.
The tool also helps traverse through UVM base classes, which is quite useful
for debugging. IDesignSpec had some more features that I will not expound
in this quick review. For UVM users who are looking for another tool to
help do UVM development and debug, it is worth a look.
---- ---- ---- ---- ---- ---- ----
Veriest VTool
A friend recommended that I go by the VTool booth and take a peek at their
offering. Veriest is an Israeli FPGA verification company and their VTool
is their GUI-based environment for general chip design and verification.
VTool helps build up an overall UVM environment and puts together some cool
documentation to show what was built -- plus it documents the resultant API.
The tool is definitely worth a look if you use UVM verification.
Current shortcoming: you have to use their GUI to map each DUT-pin to each
interface signal. If you have 1,000 signals, this is going to be quite
tedious. I mentioned that engineers would probably prefer to put together
a text file or spreadsheet to do the mappings and have the VTool read that
file and skip that tedious step. They are considering the request.
WARNING: The VTool web page does not really describe what their tool can do.
It's mostly flash and glitter. You will have to contact Veriest directly if
you want useful technical details on what VTool does.
---- ---- ---- ---- ---- ---- ----
Cadence/Forte
Last year at DAC was the first time in many years where I did not visit the
Forte booth for an update on their tool.
> Cadence Stratus HLS takes in untimed SystemC/C/C++ to generate Verilog
> RTL that Design Compiler or CDNS Genus can easily digest. The rumor
> is it's 90% Forte Cynthesizer with 10% old C-to-Silcon; a weird hybrid
> of the two tools. Samsung, LG, Sony, Realtek, Toshiba, Ricoh users.
> (booth 3515) Ask for Brett Cline. Freebie: Denali party tix
>
> - from http://www.deepchip.com/gadfly/gad060515.html
This year, I first talked with Mark Warren (from the Cadence C2S team) and
later met with Brett Cline, Mike Meredith, and Sean Dart -- former Forte
guys, now part of Cadence.
Last year at DAC, Cadence was showing the Forte tools and C2S tool and tried
to differentiate them was a confusing mess. Recently, Forte Cynthesizer was
combined with C-to-Silicon into a new product named "Stratus".
Brett mentioned in the past some customers would not use Forte Cynthesizer
because it did not have a good ECO flow -- which was available on C2S. Now
Stratus HLS uses ECO technology taken from the old CDNS C2S along with the
scheduling algorithms from Cynthesizer. This new ECO-mode can also use the
Encounter Conformal ECO Designer product for RTL to gates.
Another interesting Stratus part was its congestion map in RCP (RTL Compiler
Physical). Stratus provides a link to RCP so that when the HLS guy runs
Stratus he can get congestion information for that architecture and modify
as needed. That is, Stratus traces the congestion back to SystemC to show
the engineer what to change before he sends a final version to PnR.
There were some other new features but those are the ones that stuck out.
For me, seeing the Forte guys and hearing their enthusiasm for the combined
product gives credibility to Cadence.
---- ---- ---- ---- ---- ---- ----
Invionics vs. Verific?
Invionics Invio appears to be a tool set to help engineers rapidly develop
their own In-House EDA tools.
I thought they were a competitor to Michiel Ligthart's Verific, but it turns
out Invionics uses the Verific parser and puts a friendly development layer
on top of Invio to help rapidly develop tools.
I have challenged the Invionics team to put together a connectivity checker
for Verilog & SystemVerilog -- and make it publicly available. If the
Invionics team gets such a tool working, I will sing their praises and
report back on their success.
---- ---- ---- ---- ---- ---- ----
Synopsys bought Atrenta
On Sunday, June 7th (first day of DAC), Synopsys announced that they signed
an agreement to acquire Atrenta. I always worry about one of the larger
companies swallowing a smaller company with great technology, but this is
probably a good fit for Synopsys. Atrenta is probably best known for their
SpyGlass linting, but they have other tools related to low power linting
and CDC, so these may be good tools for Synopsys to acquire.
The Atrenta team seemed to be upbeat about the announcement.
---- ---- ---- ---- ---- ---- ----
Sell To The Engineers At DAC, Not Their CEOs!
I've notived at DAC how the EDA vendors put together demos and testimonial
theatre presentations for high-level tool capabilities -- but they seem to
have forgotten the average engineer who would just like to learn a few cool
tricks with each vendor's tools.
Instead of pitching their SW to the CEOs of Intel and Broadcom, every vendor
at DAC should hold sessions with cool TECHNICAL SystemVerilog and UVM tricks
that can be done with their tool. I would love it if each vendor included
sessions showing the Best Known Methods (BKMs) to display UVM transactions
in waveform viewers using their tools. If the EDA vendors would show BKMs
in their booths, it would draw in hands-on engineers to see what they can
do; instead of yet another sales pitch to their CEO.
---- ---- ---- ---- ---- ---- ----
DAC Attendance & Venue
I don't know what the attendance numbers were for the technical sessions
because I don't attend DAC for the papers. I attend DAC to talk to vendors.
The vendor exhibit floor seemed to be very busy this year. Since so much
chip design is done in Austin, I like the idea that they added it as one
of their standard venues. I'm looking forward being in Texas next year.
- Cliff Cummings
Sunburst Design Provo, UT
---- ---- ---- ---- ---- ---- ----
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Cliff Cummings has 22 years experience in RTL verification and synthesis training -- and is a founder of SystemVerilog and UVM.
He's won 15 SNUG "Best Papers Awards" out of 41 conference talks he's given since 1993. He looks older than this pic shows.
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