( ESNUG 554 Item 3 ) -------------------------------------------- [12/10/15]
Subject: The untold parts of that IMEC "world's first 5nm tapeout" story
FUN NOTE: Yesterday Imec just taped out the world's first 5nm chip.
Poor Aart. I'm sure he's quite furious about this. Imec used only CDNS Innovus. Aart's ICC and ICC II weren't involved! OUCH!
- intro comment on DeepChip.com email blast (10/08/15)
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Editor's Note: I received 24 tech questions from DeepChip readers
asking about this IMEC 5nm tapeout. After doing some considerable
snooping, here's what I've found... - John
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"Hi, John, Do you know the general specs of the 5nm Imec chip? How many instances? What clock? What percent memories? Why type of memories?"
"Do you know the rough specs? How many instances? How many blocks? How many clocks?"
"When's first silicon? Their press release doesn't say."
"How many different clocks? What speeds?"
"Do you know why didn't they use an ARM core? Was it an ARC or Imagination CPU?"
"What specific core did they use? The press release doesn't say."
"Was this an ARM chip?"
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The best guess was this 5nm test chip was an instantiation of a quad version
of the old Imec spin-off "Sirius" ASTRA/DIRAC DSP chip design plus an added
ARM Cortex-M0 as a bus microcontroller plus two on-chip 16 kbit SRAMs. The
chip runs at 1.25 GHz. The on-chip bus is 32-bit AHB-Lite.
The quad DIRAC was roughly 240 kcells, Cortex-M0 13 kcells, and the two 16k
SRAMS are 32 kcells -- giving a total ~285 kcells for the Imex test chip.
If this guess is right, it explains why Imec was so evasive in their press
release about their 5nm design. It's NOT a big sexy Snapdragon 810, instead
it's an old 1999 CDMA cell phone chip design from a defunct Imec spin-off,
Sirius Communications NV. It's NOT a hot zippy Cortex-A72, instead it's a
old tiny Cortex-M0 -- the smallest CPU that ARM makes. And it's all running
at a slow 1.25 GHz clock. So the Imec folks are probably thinking this
might not make for impressive PR in their minds. (But I think they're wrong.
This is about 5nm. As long as their 5nm test chip was somewhere near a
realistic design -- which this is -- it's OK. This is about 5nm!!!)
And concerning the "when is first silicon?" question, I can't get an answer.
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"I do verification. I'm curious how IMEC verified the 5nm chip functionality. Did they use UVM? SystemVerilog? Specman? Which emulator(s) did they use?"
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The idea of this 5nm test chip was to use a realistic wireless design to
test the physical differences between 3 competing forms of patterning.
- EUV, which TSMC/Intel/Samsung are testing for 10nm;
and depends on if ASML can make 10nm EUV work.
- EUV plus self-aligned quadruple pattering (193i),
with SAQP being TSMC/Intel/Samsung's backup plan
for 10nm if ASML can't make pure EUV work.
- SAQP with LE3, which is pure 5nm research.
Since this chip was about these three different approaches to interconnect
layer patterning, it only involved M2 and M3 -- M1 and V1 were dummy metal.
So, to answer this question, no UVM, no SystemVerilog, no Specman, and no
VCS/Questa/Incisive nor Veloce/Palladium/Zebu was used.
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"Who's DRC/LVS flow did Imec use? Calibre? How many violations at the beginning? How many at the end?"
"Was this Calibre or PVS?"
"How many design rules are in a 9T 5nm deck?"
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My sources say that Mentor Calibre was used for the final DRC sign-off on
this test chip. That is, there was no Cadence PVS used whatsoever.
I can't get data on how many violations Calibre saw during initial PnR.
But I've heard Calibre wasn't stressed and didn't have long runtimes on all
three chips. The idea was to find the patterning that gives reasonable
utilization without excessive manufacturing issues.
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"Our Synopsys contacts say that this 5nm Imec chip used a mix of ICC2 and Innovus PnR. Is this true?"
"Was this a full Cadence-only flow? Can you please delineate the entire PD flow?"
"I heard layout was done block by block using IC, ICC II, Innovus, Atop, Olympus to test litho of each."
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My sources tell me that this was purely a Cadence Innovus P&R chip. It was
not a mix of SNPS ICC (nor ICC2).
1. P&R in Cadence Innovus
2. Timing in Cadence Tempus
3. DRC in Mentor Calibre
4. Extraction done in Calibre xRC and possibly Cadence Quantus
Neither Atoptech nor Olympus-SoC nor ICC/ICC2 P&R were involved in any way.
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"What timining analysis? Cadence Tempus or Synopsys PrimeTime?"
"Did the Imec designers correlate the PrimeTime vs. Tempus timing on this chip?"
"Was STA in Tempus? Or PrimeTime? Did they try any timing ECOs?"
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My spies tell me that PrimeTime wasn't used anywhere on this test chip. It
was purely Tempus for all timing analysis and final sign-off.
(Which makes sense. It was an Innovus chip -- plus the fact Tempus was
architected with new crazy stuff like multipatterning in mind -- vs. SNPS
PrimeTime, architected over 20 years ago, having to add multipatterning.)
No timing ECOs were done.
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"Was chip finishing done in Virtuoso? Where there any AMS parts?"
"Do you know about the 9T library? I know it's not a TSMC lib.
Is it a GlobalFoundries lib?"
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Yes, both the Imec 5nm std cell lib development plus the 5nm chip finnishing
were done using Virtuoso.
The weird news is I'm hearing it's a FinFET chip -- and neither lateral
nanowire nor vertical nanowire -- which Imec puts on their 5nm roadmaps.
The "9T" is shorthand for a "9-track" std cell library were each cell has
9 routing tracks over/through them.
For a sense of how these range, Synopsys Virage std cell libraries come
in 7-, 9-, and 12- tracks. ARM Artisan 7-, 8-, 9-, 10-, 12- tracks. And
Dolphin Tech sells 6-, 7.5-, 9-, 10.5-, 12-track libs.
In general, lower tracks mean less area, less speed, less power; conversely
higher tracks mean higher area, higher speed, higher power. When Imec said
their 5nm std cell library is 9-track, they were saying it's a medium area,
medium speed, medium power design.
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"Can Ansys even do IR-drop/EM at 5nm?"
"No mention of Redhawk nor Voltus in the press release. Which was used?"
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From what I can find out, the Imec team didn't bother to do and EM/IR-drop
analysis on this chip, so no Redhawk nor Voltus claims of fame here.
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"Was this FinFET or lateral nanowire or vertical nanowire? What extraction tool was used?"
"Star-RC Ultra or Quantus QRC?"
"Can you find out about the multi-patterning and color variation extraction on this?"
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I'm getting conflicting data here. Some say extraction was done using only
Calibre-xACT; while others say that both Calibre-xACT and Quantus-QRC were
used. I can't get this resolved.
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SO WHAT'S THIS MEAN?: Yea, I agree this 5nm Imec 285 kcell tapeout of a
15 year old CDMA design wasn't of a big sexy fully functional chip.
But neither was the Wright brothers' first flight big or sexy -- which was
basically a large powered kite that carried one man 10 feet off the ground
for 852 feet in 59 seconds. But the fact that it was a "first" is big.
Hell, 5nm is 25 silicon atoms wide. And they're designing chips there!?!
I gotta give credit to the Imec, Cadence, and Mentor folks for pulling
this "first" off. Plus I was impressed they used just the present 2015
generation of EDA commercial PnR/DRC tools to do 5nm with. Well done.
- John Cooley
DeepChip.com Holliston, MA
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