( ESNUG 560 Item 1 ) -------------------------------------------- [04/29/16]

Subject: What's REALLY up on new CDNS Virtuoso ADE and SNPS Custom Compiler

From: [ A Little Bird ]

Hi, John,

Let's start with the ADE announcements.  Tom Beckley hasn't changed Virtuoso
itself, just his ADE.

Virtuoso ADE is the defacto standard for analog design entry and GUI for
SPICE simulation.  CDNS, since IC 6.1, has broken up the task between what
are essentially "nominal" SPICE runs (one specific condition and debug) and
"multiple" SPICE runs (corners, sweeps, Monte Carlo).

THE L-XL-GXL SPLIT THAT ANGERED USERS

Since 10 years ago under Mike Fister's reign, they (CIC division) were
forced to implement a 3 tier pricing model, they also added customer
confusion by putting:

  - ADE-L as nominal/sweep,
  - ADE-XL as corners/MC/multiple tests/spec comparison, and
  - ADE-GXL as optimization/links to layout/advanced statistical/other.

plus having a token system that upcharged the user on a daily per-use basis.

Of course it costs more money as you go from L->XL->GXL.  Customers had,
in IC 5.1.41, nominal/corners/sweeps/monte carlo without token games being
played on them.  It was always a point of contention that this break
happened.  And on top of that issue ADE-XL had a different use model than
ADE-L -- and ADE-XL really felt like a separate tool for what is a natural
task that belongs all together.

This also opened an opportunity for competitors like SNPS in custom.

WHERE CADENCE'S NEW ADE WINS

First off, every customer will be thrilled to hear the CDNS token system is
going away.  That's assuming CDNS just doesn't replace it with yet another
per-use daily tool rental game.

Then I suspect these two new parts of the ADE will do well:

ADE Explorer waterfalls the old ADE-XL capabilities into the lower level
tool (although there is some sort of upcharge and I don't know any details
on that).  So overall ADE Explorer is what was the old ADE-L, but it has
nominal/corners/sweeps/monte carlo/spec comparison now all in the same tool.

Beckley also streamlined some use issues in ADE-L in ADE Explorer.  This is
likely to prove popular.

ADE Assembler has multiple tests/statistical (from GXL).  Multi tests are
not that widely used, although popular in some circles.  CDNS wants to
propose you make a plan at the assembler level that can be extended to
verifier.  It's a bit fuzzy as to what that line is.  They seemed to have
packaged the design documentation here... mostly this is just repackaging
also.

WHERE THE NEW ADE GETS IN TROUBLE:

ADE Verifier is a project level view and is a new piece.  To quote the CDNS
whitepaper:

    "It provides high-level overview of an entire design, linking high-
     level requirements such as power consumption, gain, and bandwidth
     to the individual tests that are being created for specification
     measurement.  Virtuoso ADE Verifier can link together a group of
     specification measurement tests across multiple designers or
     locations and provide the pass/fail status in one easy-to-read
     window.  The Virtuoso ADE Verifier can also quickly identify
     requirements that have no assigned measurements, and offer visual
     clues if too few tests are linked to a particular measurement."

In this whitepaper, the problem statement was pretty accurate.   It is the
tool implementation that is a question mark.  Historically, CDN has pitched
the need for up-front planning and metric-based approaches.  For digital
chips, Incisive has this built-in with its verification methodology.  The
issue though is in digital you have code coverage and verification teams,
with self diagnostic testbenches which makes a plan pretty straight forward.

In analog design, it's all about taking system budgets to higher level
requirements, and then making individual custom pieces and deriving their
metrics and specs from that.  Typically this is done at the block designer
level, and often isn't understood for each custom block what the specs and
measures are higher up.  A lot of trust is supposed.

Making an analog/AMS topdown plan sounds good, but there are big questions
as to what it will capture up front?, and then really what progress should
a project lead engineer want to track?, and what in fact is to be tracked?

Analog is much more ad-hoc, and will continue to be so, so really any such
approach along these lines is going to have to be very flexible in tuning
this capability and not have a significant overhead.  Analog designers do
not like any intrusion for the most part -- although CAD teams love the
concept -- since it plays to a mythical overall arching meshing of the both
the analog and digital worlds together.  Some of the larger CAD teams love
big, potentially power inducing academic-level projects.

I think Beckley trying to convince analog/AMS designers to do planning is
where the new ADE may or may not fail.

    - [ A Little Bird ]

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From: [ The Mouse That Roared ]

Hi, John,

Yes, this announcement by Beckley is only on changing his ADE environment.
From what I can see, his core Virtuoso layout hasn't fundamentally changed.

IT'S BECAUSE CDNS EAD FAILED

As a first failed CDNS attempt at Virtuoso analog graphical support, a few
years ago CDNS launched EAD, their Electrically Aware Design concept.  The
idea was to reduce ECOs due to very slow Virtuoso layout implementation
performance.

  "Virtuoso Layout Suite EAD represents a big leap forward for automating
   custom design, enabling layout designers and circuit designers to work
   together more efficiently and effectively through greater real-time
   visibility into electrical issues."

       - Tom Beckley, CDNS analog/full custom bigwig 3 years ago on
         the launch of Virtuoso EAD.  (CDNS PR 07/10/2013)

In theory EAD was to provide an online review of EM/IR during your layout
creation, so your final layout (after placement of devices and connectivity
routing) was close to SPICE-expected performance.

I have yet to find any user report that EAD had worked as advertised.

The new ADE Explorer, Assembler, Verifier announcements is a second attempt.
Beckley has to speed up his ADE graphical functions because on-screen design
data density grows exponentially in lower nodes with many metals.   It's now
a driving factor in the new IC releases.

If Explorer and Assembler run significantly faster, they'll be big hits.

It will be interesting to see if Tom Beckley can convince 20 year veteran
analog block designers to buy into that "plan ahead" mindset that his new
ADE Verifier is selling.  (I have my doubts.)

The new ADE runs with Spectre and BDA AFS (I suspect because of the lawsuit
settlement.)  I don't know if it runs with either Silvaco nor any of Aart's
8 flavors of SPICE or not.

CORE VIRTUOSO LAYOUT UNCHANGED

Because not many users used the XL version of Virtuoso, not understanding
the benefits, Cadence spent some calories to make the transition from
L to XL worthwhile.  I suspect connectivity extraction and the existence
of Pcell models will drive more users to XL now...

Going to Virtuoso GXL and all the smart ModGen structures (including their
Space-Based Router) should make the layout a breeze.  The problem is that
by the time this is all ready users have different custom layout problems.
One is FinFET templates and their design rules considerably slow down
layout implementation.  So now Beckley worked on a new ADE environment for
that, including template-based DRC finding and replacement. 

Overall, it is more of the same with some minor ADE advancements, but no
big new revolutionary flow nor results.

    - [ The Mouse That Roared ]

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From: [ Elvis Has Left The Building ]

Hi, John,

Two observations:

First, Cadence ADE continues to be our "go to" tool for our analog designers
to drive SPICE simulation.  We've lived through the many generations of
Cadence product evolutions: from CDNS Composer and Analog Artist; to CDNS
ADE 5; to CDNS ADE 6 -- and now it's ADE Assembler/Explorer/Verifier. 

As best as I can tell, it looks like Tom Beckley had his R&D just repackage
ADE L/XL/GXL into what his AE's are claiming to be an "easier to use" flow
with some minor enhancements. 

Our CDNS sales guy is saying CDNS will keep selling and supporting the old
ADE L/XL/GXL tools as well, so our guys can choose the packaging we prefer.

I'm not sure if CDNS is doubling their R&D team or spreading them across
more products, now that ADE R&D are going from developing 3 to 6 products.

Second, ADE Verifier should really be named ADE Planner.  The entire analog
world has been talking about pre-planning analog designs for 20 years now.
None of the analog designers either want nor trust such tools.

    - [ Elvis Has Left The Building ]

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AND ABOUT AART'S BIG "CUSTOM COMPILER" LAUNCH AT SNUG'16

From: [ A Little Bird ]

Polygon layout is normally done by layout designers, who have a very deep
aversion to any automation at all and are very sensitive thinking their
job will go away.  Custom routers have come and gone, and topology based
approaches -- all sort of road kill.

In order to automate you must have some sort of regular structure.  Memories
play well here, or any array structure that has some sort of repeatability;
but that's a narrow market.

Reading the SNPS press releases has me believe that Custom Compiler is an
extention of SpringSoft Laker (which is popular in Asia where memories are
done) with some of the failed Ciranova Helix stuff that Aart bought in
2012 tossed in.

The fact that it's 28nm FD-SOI plus it hooks into ICC digital PnR makes it
look like Aart is trying to position this an IoT tool more than something
he wants to kill Virtuoso with.

    - [ A Little Bird ]

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From: [ The Mouse That Roared ]

Hi, John,

Let's start with history to see from where is all coming.

BECAUSE AART'S CUSTOM DESIGNER FAILED

A few years ago Aart's R&D created Custom Designer, which had the look and
feel of Virtuoso but with added features that Virtuoso lacked.  It was like
a superset of Virtuoso.  Even though it was somewhat backwards compatible
with CDNS Virtuoso, a SNPS Custom Designer failed to get customer traction.

Then Synopsys bought a few companies that had analog tools:

  1. SpringSoft - for the Laker full custom family of tools
  2. Ciranova - for the Helix placer, highly advertised as
                "the best for analog".
  3. Magma - for many things but also for full custom layout had

      a. A good polygon tool
      b. A confident and powerful custom router
      c. A compaction tool capable to work with ECOs
      d. An all "migration" environment which was actually AVP
         from Accelicon (an automated floorplaner at Pcell level)
         plus circuit optimization from the original Barcelona
         Design/Sabio Labs development.

Custom Compiler is probably Aart's first effort to consolidate features from
all these enumerated tools. 

AART'S ST 28NM FD-SOI CLAIM

The marketing story is "almost" true.  ST does use Custom Compiler for 28nm
FD-SOI, but ST has many many more teams working in many other technologies
including CMOS and advanced FinFET.  The rest ST still uses the Cadence ADE
environment and Virtuoso for layout, and Mentor Calibre for verification; so
this ST 28nm FD-SOI Custom Compiler announcement is a small step towards
winning some seats in ST.

AART'S CUSTOM COMPILER

Custom Compiler is a new full custom environment that has some "assistant
features" for the user.  First priority is to assist the layout engineer for
placement and routing activities.  But how?  For a full custom environment
specifically for analog, templates are important.  The philosophy is that a
few experienced people develop the templates that become available to all
users, including the junior engineers.  Nothing new under the sun here.

But in this case the new Customer Compiler is using the Laker engine, that's
been tweaked for "architecture exploration".  The layout engineer gets a
simple symbolic editor that reads the existing layouts (or the templates)
available for a required architecture, and then he/she can play with the
floorplan.  Once happy with results, the polygon editor outputs the Pycell
level implementation instantaneously.

Custom Compiler took this to a new level by providing additional features
from the old Customer Designer environment by connecting SPICE simulation
and verification engines with it.

The Custom Compiler placement engine has some Ciranova Helix "features and
templates", DRC, EM/IR, and parasitic extraction are all running in the
background (STAR tools) to help the user decide if this the optimal solution
or to help generate other solutions.  Same idea for routing (where EM and IR
are even more important.

In short, Aart's new Custom Compiler smells like Laker's last development,
plus some Ciranova Helix, plus a place and route schematic-based environment
thrown in.  To sell this into a very entrenced Cadence ADE and Virtuoso
customer base will be an all uphill battle for SNPS.

I don't think Tom Beckley's job is at risk any time soon.

    - [ The Mouse That Roared ]

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From: [ Elvis Has Left The Building ]

Hi, John,

SNPS recently announced their new Custom Compiler.  It looks like this just
replaces Aart's failed Customer Designer SE/LE products.  I see this as SNPS
mostly trying to go after CDNS Virtuoso Layout tool itself with a repackaged
Laker engine.  (Good luck!)  SNPS Customer Compiler also has a schematic and
simulator environment to compete with CDNS ADE.  The feature set is not
close to what CDNS has though.

    - [ Elvis Has Left The Building ]

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PYXIS, TANNER, BDA, PULSIC, SOLIDO, SILVACO...

From: [ John Cooley at DeepChip.com ]

Hey, Guys,

For completeness can you give some opinions on the other ADE's and analog tools that play in this space? For example, what about Pulsic or Tanner or Berkeley or Silvaco or...?

    - John Cooley of DeepChip.com

From: [ The Mouse That Roared ]

OK, here's my thoughts on two of them

Pulsic

A hidden gem in full custom layout is Pulsic. They always had a presence at
the analog block generation level and they recently entered in Analog/RF
at the cell level with Animate. 

Animate's automating layout is an old revolution in thinking, very similar
to the old Cadabra flow and old Barcelona Design layout synthesis -- if some
of you are old enough to remember.

From a normal analog schematic that has devices and connectivity, Animate
creates up to 500 options of placement and routing.  If you have constraints
for placement or routing, all of it's solutions will obey ALL of them!  The
user graphically or text choses a few of them and starts modifications.

All support is online graphical and the user can generate fixed or "soft"
templates, can break the routing, and redo it again with different metals;
all in an assisted environment. 

The appeal of this approach is that you can spend 5 minutes to get to one
solution, but at each step you can save the "status", and if you don't like
the end result can go back and build another version!  You have to see it
to understand all of it!  All this while DRC and LVS are respected 100%.

Right now Animate doesn't have a full ECO capability, but I suspect they'll
eventually add it.

Mentor Pyxis and Tanner

As we all know the Pyxis acquisition did not bring Mentor more successful
market penetration with all that effort to be OA compatible.  You cannot
make a full analog design environment from just a router without serious
investment and apparently the Pyxis direction now is MEMS.

Even so, the MENT Tanner purchase brought in some new customers.  They are
mostly low end design or small companies who always wanted cheap tools.  So
other than Sawicki adding Calibre LVS/DRC into the Tanner custom layout not
much news in this Mentor camp.

Berkeley

BDA had its own ADE equivalent called "ACE".  I have not seen it since it
first launched at DAC'13 three years ago.  (ESNUG 524 #2)  Did ACE get
discontuined as part of the Cadence/BDA lawsuit settlement?

Silvaco Expert Layout

They only do 65nm to 45nm range layout.  Too primative for our needs.

    - [ The Mouse That Roared ]

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From: [ Elvis Has Left The Building ]

MENT also has an ADE alternative called Analog Characterization Environment
(ACE) which they got from their BDA acquisition.  It's promising, but also
missing the full CDNS ADE feature set.

Other tools in our front-end custom IC flow:

SPICE Simulators: CDNS Spectre, CDNS Spectre XPS, MENT BDA AFS, SNPS HSPICE,
SNPS FineSim, Keysight GoldenGate.  Our analog, RF, memory and std cell
designers use different simulators depending on their:

                       speed vs. accuracy vs. capacity

requirements for the node they are working on.

Variation: We have standardized on Solido.  We like that we can use Solido's
environment with designs in CDNS ADE or netlist designs, depending on what
our analog, RF, memory, std cell designers prefer.  (Works with any SPICE.)

Other custom design tools we have EDA sales guys calling us about:

Silvaco SmartSPICE: They say they have put R&D to improve their simulator.
We haven't evaluated it yet, but plan to.

CLK-DA: I heard that they have a good characterization tool, but saw that
they are not exhibiting at DAC this year when putting together my own DAC
must see list, so not sure if they are in trouble.

Runtime-DA: They have a SPICE simulation job scheduler which looks promising
that we are planning on evaluating.

    - [ Elvis Has Left The Building ]

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  EDITOR'S NOTE: If you're an Analog/AMS/full custom layout engineer and/or
  a SPICE user -- and if you found this actual analysis of the news useful
  (instead the usual paid regurgitated company press materials) please call
  me at (508) 429-4357 and leave your name and cell number.  I'm trying to
  develop some more anon informants in analog/AMS/custom.  Thnx!  - John

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)