( ESNUG 560 Item 5 ) -------------------------------------------- [05/06/16]
Subject: Calypto Badru says Sanjiv Kaul left due to "vision differences"
Although rejoining Daddy MENT is mostly just an org chart change (since MENT
already has a 51% stake in Calypto), I still don't 100% believe this rumor.
Sanjiv Kaul even got a Catapult business deal with Google and Google even let
Calypto publically brag about it??? (How often does Google let *anyone* use their name for *anything*???)
My sources also say that after the deal is closed, Badru Agarwala, the
former CEO of Axiom -- which got acquired by MENT in 2013 -- will be the
new GM in charge of the Mentor Calypto business unit. My guess is that the
"Calypto" name will probably very quickly go away, but that Catapult, SLEC,
and PowerPro will keep being called what they're called now.
- from http://www.deepchip.com/items/0552-01.html
From: [ Badru Agarwala of Mentor Calypto ]
Dear Mr. Cooley,
I've seen you write 3 different references to the Calypto-MENT transition
on DeepChip and you simply will not let it go. Enough is enough.
Yes, I was the CEO at Axiom. That much is true.
The reason why Sanjiv Kaul left when Mentor acquired Calyto was not due to
any of your crazy conspiracy theories, John. You may think what I'm about
to say is B.S., but it's true.
Sanjiv Kaul left because we had very different visions as to the direction
Calypto should take now that both Cadence and Synopsys are both so weak
in the High Level Synthesis space.
I've spent the last 6 months talking to potential and existing customers to
validate my vison and the greater majority of them agree with it.
BADRU'S HLS "VISION"
Two major takeaways I got from customers who use (or want to use) HLS:
1. Time to Market. The #1 reason to do C/SystemC/C++ based design
is it gets your chip done much more quickly than the standard
hand RTL techniques do.
2. Make HLS more like RTL. The older RTL-based designers will be
more comfortable with C/SystemC/C++ based design if that flow
mimics the old RTL flow that they know. This is especially true
for RTL design groups thinking about switching to C/SystemC/C++.
It's to this vision is where Calypto R&D is currently executing on for our
upcoming software releases over the next 18 months.
Expect to see:
- SoC designs mixing blocks of Verilog/SV with C/SystemC/C++.
Use RTL in blocks where it works best. Use HLS in other blocks
where it works best. HLS is best where architectural tradeoffs
are more important. RTL blocks for code reuse or where hand-
crafted aspects are needed. Design hierarchy will decide which
block is which -- and expect the Calypto HLS platform to support
mixing these blocks freely.
Warning: Amdahl's law still applies here. You need to have at
least 60% of your blocks in C/SystemC/C++ to get significant
design and verification speed-up. If you only do 10% of your
chip in C/SystemC/C++, it will not be sped up.
- new C-based HLS tools that are like RTL tools. These will be:
- Rules-based design checking (linting) to catch coding
violations in your C code.
- Formal checking in your C code.
- C-to-RTL equivalence checking (SLEC but better!)
- Ability to handle ECOs in your C code.
In addition, the RTL generated by HLS should seamlessly fit into
existing MENT/CDNS/SNPS RTL signoff flows so that none of the
productivity gained by HLS is lost.
- C-based HLS tools integrate to existing RTL verification flows.
- works with assertion-based methodologies
- works with functional coverage methodologies
- works with code coverage (such as line, branch,
and state)
And the reuse of HLS verification methodology in the RTL flow.
- Predictable verification closure metrics that are familiar to RTL
designers and that provide confidence that the design is verified
and confidence in the synthesis process itself. Compared to an
RTL flow, Catapult users today see a 30x-80x verification speed-up,
faster development, and debug with 6-10x fewer lines of code.
- C-based HLS tools will integrate with power reduction tools
to generate RTL that is highly power-optimized.
- These C-based HLS tools will have strong native debug and
visualization features to understand design violations,
changes, and coverage analysis.
And more importantly these C-based HLS analysis tools must mean the user
gets quality HLS results without being an expert.
Just like in RTL, it is my hope to also get an IP ecosystem that brings
RTL designers up to speed on HLS. We will need an exchange of reusable HLS
components and IP developed in both un-timed C++ and timed SystemC just like
how designers have now for RTL.
I hope to have these new HLS tools ready over the next 18 months. Or to
give you a specific deadline, John, because I know how you like deadlines:
by December 31st, 2017 these new Calypto HLS tools will be done.
Are you happy now, John?
- Badru Agarwala
Mentor Calypto Fremont, CA
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