( ESNUG 562 Item 1 ) -------------------------------------------- [06/30/16]

Subject: Marmaduke gives an AMS circuit designer's Austin DAC'16 Trip Report

    - [ Elvis Has Left The Building ]
      http://www.deepchip.com/items/0560-01.html

From: [ Marmaduke ]

Hi, John,

Please keep my name and company anonymous.  Either I can be anon and tell
the truth, or I can be public and say what the EDA vendors want me to say.

I prefer to go by the name "Marmaduke" if possible.

First off, I'd like to congradulate you, John, on interviewing those three
analog designers to get their thoughts on Cadence's new Virtuoso ADE launch
plus Synopsys' new Custom Compiler launch.

Plenty of EDA blogger web sites regurgitate what the EDA vendors marketing
departments publish.  DeepChip is the last remaining site that actually does
a critical analysis from the users' perspective of the EDA news.  Thank you
for doing this service for the industry.

     What's REALLY up on new CDNS Virtuoso ADE and SNPS Custom Compiler
                 http://www.deepchip.com/items/0560-01.html

But from reading their comments, it was clear to me that all three of your
sources were full custom designers.  What's missing was the AMS viewpoint.
So in that vein I would like to share with you how an Analog Mixed Signal
chip designer like myself saw at the Austin DAC earlier this month.  Our
outlook on EDA tools is somewhat different because we do simultaneous
SPICE + digital simulator runs to simulate our AMS designs.  We live mostly
in the analog design world with some hooks into the digital design world.

First off, although 16nm, 10nm, and 7nm are hot news for digital designs,
most AMS work is done at 65nm or 45nm.  So when I saw TSMC promoting that 

    "Cadence and TSMC also validated a custom/mixed-signal design
     reference flow for the 10nm process."

         - Cadence press release (03/15/2016)

It was Tom Beckley aiming at getting (or more likely keeping) his Virtuoso
business with either Apple, Qualcomm, or Samsung smart phones.  Otherwise
the vast bulk of AMS chip design is not done anywhere near 10nm.

Secondly, I think it's important to discuss both big-A/little-d and the more
common little-A/big-D designs being done today.

So, before booking my overpriced direct flight to AUS on Southwest, for my
management I created my pre-DAC AMS shopping list:

My management also created a list of questions that they wanted answered
from this DAC.

MY 5 BIG AMS QUESTIONS TO BE ASKED AT THE AUSTIN DAC:

  1. Is there a viable rival to Virtuoso?  Does anyone have a realistic
     shot of displacing Cadence as the primary tool for AMS data entry,
     AMS physical layout, and the AMS database for AMS designs?

     a. Legacy designs live a long time for analog and provide valuable
        IP as starting points for our new designs.  Sure GDSII ports
        easily but smart connectivity such as Pcells are problematic.
        Slight changes in how cells are built can create real problems
        that are challenging to find.

        Rule of Thumb: if an analog block works, you don't touch it!

     b. Cadence open AMS interoperability historically provided an easy
        access (no pun intended) to adding workarounds and/or point
        tools to problems that Cadence AMS R&D didn't anticipate.
        This flexibility is critical in a market as diverse as analog.
        The recent moves by Tom Beckley seems to be moving away from
        this idea of an analog ecosystem and instead preferring an
        all-things-come-from-Cadence behemoth.  Nevertheless, most
        reasonably sized analog houses have years of analog flows
        built around the Cadence Virtuoso franchise.

     c. Cadence is the defacto AMS signoff tool for AMS PDKs with the
        foundries.  We know from watching Innovus/Voltus it's possible
        to move the foundries (with enough customer support and some
        very compelling PnR technology) but AMS PDKs are expensive to
        create and maintain and a they're cost of doing business (as
        in they don't make money).

  2. Do my best-in-class AMS tool pieces work together well?  Or will
     my AMS runs miss the very problems I'm trying to find?  The behavioral
     models and SPICE engine tricks used to speed-up SPICE runs can also
     mask AMS issues.

     a. Which EDA vendors speed-up SPICE vs. playing games that give
        the illusion of speed-up while hiding AMS bugs?

     b. Who is helping the "analog modeling challenge"?  I can write
        a terrible non-convergent model in 5 min.  Who's helping me
        create fast convergent models?  Don't even get me started on
        keeping models up-to-date or deciding what needs to be modeled
        and determining if the model is right...

     c. How do I move around between all the design representations?
        From Verilog-A for the SPICE simulator to Verilog-AMS and real
        number models in the AMS simulator to SystemC-AMS and other
        high-level system tools?

     d. Monte Carlo, variation-aware, statistical design, PVT, or
        design of experiments -- whatever you call it, exploring
        corners and sigma in the AMS design space is crucial -- and
        there are so many ways to do it poorly...

     e. AMS data management because there are Gigabyte's generated
        daily that needs analyzing, sifting, and storing.

  3. Has automated analog layout come true yet?  Tom Beckley promised
     this with Neolinear back in 2004, but NeoCircuit didn't deliver.
     Is there someone else who can deliver automated analog layout?

  4. Does anyone in AMS have something new?  All the market leading
     SPICE, environments, and layout tools sit on really old software
     technology and architectures from the 1990's.  Is anyone tackling
     the problem COMPLETELY differently?

  5. Is there anyone cheaper who can do the AMS job well?  For an AMS
     house to buy a full Cadence suite costs more than most circuit
     designer's annual salaries.  Have either Silvaco or Mentor Tanner
     now crossed a threshold to be useful on mainstream AMS designs?

We're an AMS house.  Notice my list doesn't even address problems like RF,
advanced nodes, accurate extraction, connecting back into big SoC's, and
system-design-plus-software, including substrates, package and board
parasitics, thermal management...  We do AMS IP blocks for big-D/little-a
chips.  I had to pick what to attack first...

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So what was my takeaway after 3 full days on the Austin DAC exhibit floor?

CADENCE IS STILL THE 800 LB GORILLA IN AMS

Concerning my #1 question "Is there a viable rival to Virtuoso?", from what
I saw at this DAC, the answer is "no".  The biggest threat to Tom Beckley's
empire is, in terms of complete solution schematic capture/layout and full
custom flow is, Synopsys Custom Compiler.   But I still don't see Synopsys
having real traction.  Mentor is lurking in the background, but I've never
had the sense that Wally has committed enough resources to make a play at
the Virtuoso sweet spot.

Based on everything I saw and limited time, Antun Domic' Custom Compiler
will not be my first priority for serious follow-up after DAC.  However,
I'm getting closer to the tipping point of at least taking a look.

Cadence announced earlier this year numerous enhancements to the Virtuoso
ADE and those products were a big focus for the analog portion of their
exhibit.  Tom Beckley seems to be trying to close gaps based on where he
sees the perceived competitive threat (or where other players getting money
for AMS).  So the new Virtuoso improvements seem to be aimed at:

  - blocking competitive threats in layout with layout performance
    improvements and improved electrical connectivity.  I'm sure
    this is largely focused with concern over Antun's plans for
    custom layout at Synopsys.

  - holding off growing market momentum in statistical design and
    simulation management (with an eye towards staving off Solido,
    MunEDA, BDA/Mentor).  I'll talk more on this topic later, but
    my guess is Cadence did not add real underlying ADE algorithm
    advancements here with the possible exception of waveform
    capacity and performance.  I think most of the improvements
    are usability and related to more easily setting up, starting,
    and monitoring large groups of SPICE simulations.  Usability
    is important but the SPICE simulation have to complete in a
    feasible amount of time (hours not days or weeks).

  - adding real improvements for AMS design at advanced nodes

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FOR THE SIDE TOOLS, ALL ROADS LEAD TO VIRTUOSO

Concerning my #2 question "do today's best-in-class AMS tools work together
well?", my answer is "it depends".

Solido vs. MunEDA

Many of the 3rd party AMS tools look at parts of AMS design or verification.
Solido and MunEDA have led the way for many years in terms of looking at how
to thoroughly explore the analog design space through statistical design.
These tools deeply focus on thoroughly examining a design at the block or
subsystem level across process, voltage, and temperature with special
emphasis on simulating in SPICE the impact of process variation.

I'm not going into a detailed technical discussion here, but both companies
add some real technology to make this exploration more efficient and more
predictive of actual silicon.  My personal preference today is for Solido. 

Beckley clearly lagged in recognizing the importance of smart statistical
design (or "design of experiments") for exploring the analog design space.
This even applies to the mature nodes.  Solido's Amit Gupta cited how the
65nm to 40nm "node jumpers" used variation-analysis to get better yield in
his 2nd annual SPICE survey.  (ESNUG 561 #4)

I don't think Cadence has closed this gap, and honestly I don't know that
Cadence should put resources here.  I'd rather Beckley focus Cadence R&D
on the database, underlying engines and connectivity across the Cadence
flows.  If Cadence actively promoted and encouraged the integrations these
companies have into the Cadence ecosystem, Cadence would sell more of their
engines and keep designers like me happily locked into Virtuoso.  Trying
to sell Spectre licenses is OK, but selling an entire AMS design ecosystem
is better.

Mentor BDA AFS memory slip

The SPICE simulators such as Mentor AFS (from Ravi at BDA), and ProPlus
NanoSpiceGiga (and now NanoYield), plus Synopsys FineSim (from Anirudh when
he was at Magma) are all interesting pieces of this puzzle.

I like MENT BDA AFS, but I want to see Ravi's engine inside a solid mixed-
signal option like Cadence AMS Designer.  I should qualify this by saying
AFS has a co-simulation option with "Verilog" simulators -- but Mentor has
the opportunity to more closely couple AFS with the rest of the Mentor
family of simulators.

I know Amit's survey talked about a Mentor SPICE usage drop (ESNUG 561 #5)
due to a drop in memory SPICE usage, but I wonder if it's really all about
Ravi's BDA AFS not being in a Mentor mixed-signal simulation flow is the
real issue?  Right now Questa ADMS includes ELDO (general purpose analog),
ADiT for fast-SPICE, and Eldo-RF as engines which all to co-simulate with
Questa (digital).  I was surprised to not see Ravi make an announcement at
DAC that his AFS was now part of the Questa ADMS mixed-signal solution.

Synopsys SPICE is not AMS friendly

Depending on how you count, Antun Domic has something like 7 to 9 Synopsys
SPICE simulators, and for an AMS designer it doesn't seem to be easy to move
among them at all.

The old Magma FineSim has a tight integration into the Cadence ADE (because
Anirudh made that so because he was at Magma at that time) -- but FineSim
has no mixed-signal integration with the Synopsys VCS digital simulator (due
to the SNPS vs. LAVA lawsuits at that time.)  SNPS acquired in 2011, yet
FineSim still isn't integrated with VCS.  Instead, Antun decided that his
VCS-AMS is to use his newer CustomSim as the analog simulator -- which also
has no integration into Cadence.

Beckley's two big AMS advantages

Tom Beckley has a real advantage in his AMS Designer from both it use model
and its ability to easily select different analog engines.  When setting up
an AMS simulation, I just specify which analog engine (Spectre, APS, etc.)
and ADE nicely handles the simulator options and netlisting.

Plus, as an AMS designer who uses both SPICE and digital simulator license
in unpredictable mixes, I like the business flexibility of tokens for the
simulators.  Tokens mean we don't have to decide (months or years ahead)
where to specifically spend our simulator dollars and fight battles trying
to figure out the detailed capacity we need by simulator (or argue with my
management why I need access to a specific engine).  Plus the need for the
engines changes over the course of the design.  Early in the design, I'm
heavily using the analog engines standalone, but as the design progresses
AMS Designer becomes the workhorse.

Hopefully Beckley appreciates these advantages!

As far as AMS Designer itself, at this DAC I didn't see any dramatic changes
from the perspective of designing in mainstream processes/nodes, but it
continues to be a nice workhorse that offers tremendous flexibility to drive
from the analog environment (from a schematic) or a more digital centric
(or regression friendly) flow from the command line.  

AMS and Verilog-A or Verilog-AMS or real number models

As I said earlier, AMS designers like myself live mostly in the analog world
but we also have connections into the digital world.  That means we mix and
match various "models" for the right speed or accuracy of our simulations.

  a SPICE simulator can handle
    - a Verilog-A behavioral model

  a mixed-signal engine or co-simulation between a SPICE engine
  and a digital simulator can handle
    - a Verilog-A model - that will be executed by SPICE engine
    - a Verilog-AMS model - part of the model will be executed
      by the SPICE engine, part by the digital simulator
    - a real number model (or Cadence WREAL) - that will be
      executed by digital simulator

  a digital simulator can handle
    - a real number model

At the end of the day, at the chip-level I still see many simulations that
find real life design problems and that run for days and weeks (on multiple
cores).  I can reduce this runtime down to a few hours by careful design
partitioning and choosing the right level of model.

However, I've also seen many cases where human operator mistakes happened in
the modeling choice prevented actual AMS design problems from being found.
Most analog engineers want to focus on the challenges of the circuit design
itself and not learn how to code a model.  Digital verification engineers
understand the concepts of self-checking testbenches, assertions, etc, but
lack the analog expertise to understand what information must be included
in a given AMS simulation.

For instance, if I abstract a part of the circuit that actually has a sneak
current path in a weird corner condition, the model either needs to flag
that particular input condition as "not allowed" or that circuit needs to
be kept at transistor level for that particular test.

Sounds easy, but it is not trivial...

The devil here is in the details in terms of performance, ease of debug, and
the AMS simulation signoff process.  From what I saw at the Austin DAC, I
can't really determine the effectiveness of all these new pieces from the
various EDA vendors until I can run some AMS designs through and use them.

Loading large simulation results into the waveform tool and finding what you
need to see is non-trivial; so it will be interesting to see the performance
of Cadence's new waveform enhancements.  In the past, other tools have
managed large amounts of data more effectively than Cadence (BDA, Synopsys,
and Solido have all offered some usability advantages compared to Cadence),
but Cadence makes the mixed-signal simulator flow the cleanest.

And I don't see anyone really solving the modeling choice conundrum.

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PULSIC ANIMATE AND INTENTO ID-XPLORE

Concerning my #3 question "Has true automated analog layout arrived yet?",
from what I saw at DAC, I plan to look more closely at Pulsic Animate and
Intento ID-Xplore.

Beckley listed numerous performance improvements in his new Virtuoso ADE
launch earlier this year at his CDNlive'16 event:

And I noticed, John, how all three of your full custom designers disliked
the ADE Verifier -- which adds planning to analog design.

    "I think Beckley trying to convince analog/AMS designers to do
     planning is where the new ADE may or may not fail."

    "It will be interesting to see if Tom Beckley can convince 20 year
     veteran analog block designers to buy into a "plan ahead" mindset
     that his new ADE Verifier is selling.  (I have my doubts.)"

    "Second, ADE Verifier should really be named ADE Planner.  The entire
     analog world has been talking about pre-planning analog designs for
     20 years now.  None of the analog designers either want nor trust
     such tools."

         - http://www.deepchip.com/items/0560-01.html

From an AMS designer perspective, Tom Beckley's refocus in automated layout
is critical to Cadence maintaining the leadership in the analog market.
Clearly Cadence is watching progress by companies like Pulsic with smart
analog routing and Synopsys for general performance of the layout editor
from Laker. 

Pulsic Animate's ability to autogenerate constraints based on the schematic
offers an impressive usability and performance advantage.  Cadence's new
ADE release improves the management of constraints plus it adds some other
usability and technical improvements for ModGens. 

I think Beckley's smart to mimic the Pulsic Animate flow (above).  If Pulsic
can sell it as a 3rd party tool, why can't Cadence sell it as an add-on?

Interestingly, Cadence got pieces such as ModGens and layout migration from
acquisitions; but some of the original research from Dr. Rob Rutenbar and
his students back when Rob was at Carnegie Mellon University tackling the
PITA problem of sizing for analog circuits.  This optimization technology
which became the foundation for Neolinear (who was acquired by Cadence)
has never been fully productized in Virtuoso.  Now signs of similar types
of technology can be found at MunEDA and another new startup, Intento. 

Intento focuses on optimizing/automating the sizing process for complex
analog functions.  It also helps port design IP across processes.

At this time, Intento's tools only integrate with Cadence.  On a related
side note, a retired TI Fellow, Dr. James Hellums, gave some analog design
talks at the Zipalog booth (an AMS verification house).  Dr. Hellums'
talks discussed why the analog sizing problem is such a headache.

        ----    ----    ----    ----    ----    ----    ----

ANIRUDH VS. ANTUN

Concerning my #4 question "Is there anything really new for AMS this year?",
my answer is "no".

There were lots of interesting improvements this year in analog design, but
nothing that seemed to indicate a significant change under the hood as far
as core technology was concerned.

John "Jolly" Lee of Ansys Apache Gear is trying to get Hadoop and "Big Data"
into EDA by way of his new SeaHawk tool; but that's about IR-drop and noise
reduction -- these are other areas I need to spend more time exploring.  I
have personally spent too much time tracking down noise issues caused by
the digital side impacting my precision analog circuits.

If Anirudh has the bandwidth to apply his drive and vision for digital to
pull in analog in the context of large SOC's and mixed-signal systems, there
may be some innovative changes.  But so far at this point, most of the Tom
Beckley Virtuoso improvements seem to be driven by the actions of the
competitors like Synopsys and Pulsic.

If Antun Domic wants to displace Virtuoso, his "new" SNPS Custom Compiler
needs to offer much more differentiation than just a simple redo of Laker
with some Ciranova Helix thrown in.

        ----    ----    ----    ----    ----    ----    ----

TANNER AND SILVACO

Concerning my #5 question "Are the cheaper AMS tools viable now?", I plan to
look more closely at Tanner and Silvaco.

Silvaco had interesting announcements at DAC with the acquisition of EdXact
and IPextreme.  EdXact offers methods to reduce the size of netlists with
extracted parasitics.  Any help on reducing simulation complexity while
retaining accuracy is important.  This particular issue of parasitics is
blowing up at the advanced nodes but always a concern for analog anyway. 

The ipExtreme acquisition certainly seems to mark a broadening of Silvaco's
footprint and ecosystem.  Silvaco looks to be connecting an analog flow
that seems to be well-suited for developing targeted analog IP that will
be embedded in big SoCs with a business infrastructure for ipExtreme to
manage and license that IP.

Silvaco has always been known for device modeling expertise (at component,
i.e. transistor level) which is a critical starting point for analog.  They
seem to have been on a concerted push to offer a full service environment
for analog and some limited mixed-signal.  The interesting twist is they're
leveraging their modeling expertise to attack advanced nodes where the
simulation problem mushrooms.

So for developing analog IP, Silvaco seems to be a serious low cost option
with capability to handle advanced nodes.  However, I'm not so sure that
I'd look to Silvaco for developing say a small AMS chip that included a
core.  For the digital side of that chip, I'd want to be able to connect
more directly into a mainstream digital implementation flow.

One real surprise for me at the Austin DAC was to see how quickly Mentor
is adding technology such as the Pyxis router and a solid integration
with Calibre for the Tanner design flow.

This is Wally putting Maserati engines inside of Geo Metros.  And then
selling them at Geo Metro prices.

I've been amazed with the speed of Tanner improvements since the March 2015
acquisition by Mentor Graphics.  The really interesting announcement from
Mentor and ARM at this DAC was the availability of a low-cost design flow
for the ARM Cortex-M0 processor with the Tanner AMS design flow.

For years, Tanner had looked like a barely viable, old node, low-cost
alternative to Cadence, but Tanner did not offer mixed-signal.  In 2013,
Tanner initially added mixed-signal support.  The combination of Mentor
Tanner with a mixed-signal solution plus ARM support is very intriguing
for designs that are cost sensitive.

Because this flow is specifically focused at MEMS, analog, digital, AMS,
it seems to be worth considering for low-cost IoT projects.  Tanner is on
my action list to try.  I'll be honest, there's a lot of risk to moving
this way, but for smaller, margin-sensitive design houses lowering design
cost can happen by large improvements in productivity (see the Cadence
discussion above) or by spending substantially less to get similar
productivity...

   - [ Marmaduke ]

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Marmaduke has many years experience in analog, full custom, and AMS designs -- and is based in Silicon Valley working on Big-D/little-A designs for companies he can't name. Like the cartoon Marmaduke, the real life human "Marmaduke" really really really likes lasagna.

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Related Articles:

    What's REALLY up on new CDNS Virtuoso ADE and SNPS Custom Compiler
    246 engineers surveyed on general SPICE use & SPICE requirements

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   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
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