( ESNUG 582 Item 4 ) ---------------------------------------------- [04/06/18]
Subject: 8 engineers give the dirt on the Cadence/Imec first 3nm tape-out
WHAT THE HELL HAPPENED?: As I often do when EDA news breaks, I did one of
my quickie user surveys about that CDNS/Imec first 3nm tapeout. But what
was weird was the first user responses were quite positive about it.
Then, after SNUG'18, the next batch of user responses went negative. (?)
Here's the timeline:
02/28/2018: Cadence and Imec issue a joint press release titled
"Imec and Cadence Tape Out Industry's First 3nm Test Chip"
03/14/2018: Synopsys announces a new panel to be added to SNUG'18
"Synopsys and Industry Technologists on the Path to 2nm"
03/16/2018: An unaware John Cooley publishes his 11 questions
"Cooley's 11 questions on Cadence/Imec first 3nm tapeout"
... where Engineers #1, #2, #3 answered my 11 Cooley 3nm questions
fairly positively.
03/22/2018: the Synopsys 2nm SNUG panel actually takes place at SNUG'18
... then Engineers #4, #5, #6, #7, #8 answered my 11 Cooley 3nm
questions fairly negatively. (?)
I know this is just a tiny user survey that has no real impact in the grande
scheme of the universe -- but I still have to ask: What the hell happened?
- John Cooley
DeepChip.com Holliston, MA
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1.) What are the general specs of the 3nm Imec chip? How many
instances? What clocks? What percent memories? Why type
of memories?
before
Engineer #1: "Press release said it was 42nm poly, 21nm metal.
Nothing about number of insts, clocks, memory."
Engineer #2: "42nm poly pitch and 21nm routing metal pitch.
1/2 M inst. 2 Gig clock. 20% memory"
Engineer #3: "As before 285 K inst, 1.25 GHz, 32 K inst mem"
after
Engineer #4: "This is EUV and SAQP testing. Much ado about nothing."
Engineer #5: "It's the old 5nm test chip ported to 3nm."
Engineer #6: "same as before, but with a 26nm metal pitch.
this is cdns making news that isn't news."
Engineer #7: "Small. Under 500 K inst. Under 1 Ghz. No mem."
Engineer #8: "I suspect it had a basic clock. This is just
for litho testing."
2.) When is their first 3nm silicon? Is Imec fabbing it? TSMC?
before
Engineer #1: "Imec. TSMC is working on 3nm for 2023."
Engineer #2: "Imec test fab only. No TSMC."
Engineer #3: "Imec."
after
Engineer #4: "Imec"
Engineer #5: "Imec."
Engineer #6: "Imec, with an eye of selling the process to TSMC."
Engineer #7: "Imec"
Engineer #8: "Imec"
3.) Is this "common industry 64-bit CPU" an ARM core chip? Or
an Imagination core? Or a RISC-V core? Who's std cell lib
did you use?
before
Engineer #1: "I'm guessing an A-72."
Engineer #2: "Single ARM 53"
Engineer #3: "Quad ARM Cortex-M0"
after
Engineer #4: "Who cares? It's a fake chip for process testing."
Engineer #5: "ASTRA/DIRAC DSP plus ARM Cortex-M0"
Engineer #6: "That old Cortex-M0 design."
Engineer #7: "A-53 or A-72"
Engineer #8: "something ARMv8-A"
4.) How did they verify the chip? UVM? SystemVerilog? Specman?
before
Engineer #1: "Wasn't done."
Engineer #2: "Didn't verify. Test chips aren't functional.
Proving manufacturability only."
Engineer #3: "N/A"
after
Engineer #4: "Don't need to verify fake chips."
Engineer #5: [no response]
Engineer #6: "nope"
Engineer #7: "doesn't apply"
Engineer #8: [no response]
5.) What emulators did Imec use? Palladium? Veloce? Zebu?
before
Engineer #1: "Not done."
Engineer #2: "Didn't verify. Test chips aren't functional.
Proving manufacturability only."
Engineer #3: "N/A"
after
Engineer #4: "fake chip"
Engineer #5: [no response]
Engineer #6: [no response]
Engineer #7: "doesn't apply"
Engineer #8: "No"
6.) Who's DRC/LVS flow did Imec use? Calibre? Pegasus? PVS?
How many violations at the beginning? How many at the end?
Why was there no mention of Cadence Pegasus DRC in the
Imec 3nm press release? How many design rules in a 9T 3nm
deck?
before
Engineer #1: "Calibre. 5T deck"
Engineer #2: "iPVS and Calibre"
Engineer #3: "Calibre"
after
Engineer #4: "Pegasus is a joke. No decks. Only Calibre works
at that level."
Engineer #5: "Calibre"
Engineer #6: "calibre with (maybe) pvs?"
Engineer #7: "Calibre. It won't be 9T. It'll be 5T single fin."
Engineer #8: "Calibre"
7.) Did Imec use a 100% Cadence Innovus PnR flow? Or was Synopsys
ICC2 involved in any way as a back-up? Or on some blocks?
before
Engineer #1: "I don't think Imec uses ICC2."
Engineer #2: "100% Innovus PnR, no Synopsys."
Engineer #3: "Innovus alone."
after
Engineer #4: "I'll bet you Imec uses both Innovus and ICC2."
Engineer #5: "Innovus"
Engineer #6: "prbly innovus only"
Engineer #7: "Innovus"
Engineer #8: "They wouldn't have done a press release without
having used Innovus."
8.) Did Imec use a 100% Cadence Genus RTL synthesis flow? Or was
Synopsys Design Compiler used in any way?
before
Engineer #1: "Officially Genus-RTL. Unofficially both DC and Genus."
Engineer #2: "100% Genus RTL, no DC"
Engineer #3: "How much synthesis does a process node port involve?"
after
Engineer #4: "Fake designs don't need fancy synthesis.
Even Genus can synthesize fake designs."
Engineer #5: "Design Compiler with Genus-RTL as backup"
Engineer #6: "prbly genus only"
Engineer #7: [no response]
Engineer #8: "I suspect Genus-RTL was used without Design Compiler."
9.) Did Imec use a 100% Cadence Tempus STA flow? Or was Synopsys
PrimeTime used in any way? How well did Tempus correlate with
PrimeTime? Did the Imec guys try any timing ECOs with Tempus
on this 3nm chip? What was used for final sign-off?
before
Engineer #1: "Tempus was tried; Primetime for the real work."
Engineer #2: "built-in Innovus PnR internal timing. No ECOs."
Engineer #3: "ECOs work well inside Innovus and Tempus."
after
Engineer #4: "I can't imagine doing ECOs on a fake chip with Tempus."
Engineer #5: "I see it as PT with Tempus as back-up."
Engineer #6: "prbly PT for sign-off"
Engineer #7: "Primetime"
Engineer #8: "Primetime owns STA."
10.) Did Imec use a 100% Cadence Voltus IR-drop flow? Or was Ansys
Redhawk / Gear / SeaHawk / SeaScape used in any way? Why was
there no mention of Cadence Voltus IR-drop in the 3nm Imec
tapeout press release? What was used for final sign-off?
before
Engineer #1: "SeaHawk with Voltus"
Engineer #2: "Voltus"
Engineer #3: "maybe Voltus? Do test chips need noise analysis?"
after
Engineer #4: "RedHawk can do IR-drop on fake chips really fast."
Engineer #5: [no response]
Engineer #6: "prbly both RedHawk and Voltus"
Engineer #7: "It wasn't in the press release because it was Redhawk."
Engineer #8: "Voltus coupled with Innovus is powerful."
11.) Did Imec use a 100% Cadence Quantus QRC extraction flow? Or
was Synopsys StarRC or Mentor Calibre xACT used in any way?
What was used for final sign-off?
before
Engineer #1: "Quantus QRC"
Engineer #2: "Built-in Innovus in-design extraction"
Engineer #3: "Calibre xACT"
after
Engineer #4: "Quantus is crap. They used StarRC if anything."
Engineer #5: [no response]
Engineer #6: "prbly StarRC and Quantus"
Engineer #7: "xACT + StarRC"
Engineer #8: "I suspect it's Quantus and they simply forgot to
mention it in the press release."
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