( ESNUG 588 Item 11 ) --------------------------------------------- [01/16/20]
Subject: Mo on tweaking your PLL/DLL for SoC vs. tweak your SoC for PLL/DLL
DAC'19 Troublemakers Panel in Las Vegas, NV
Cooley: Mo?
Mo: Yes, sir.
Cooley: Speaking of going against incumbents, when I ran the video of
you last year talking about PLL's and DLL's, I got a very angry
letter from a company called True Circuits.
How do you fight in a world where you're the small guy?
Mo: Well, I mean the whole design space is shifting, right? As
Joe Costello said, he wants to customize his processors, and
then the PDKs are very difficult.
So there are two ways we at Movellus compete with these TCI
guys -- or incumbents in general with off-the-shelf IPs.
And that is this: if you buy off-the-shelf IP, you are
typically changing and customizing your own design to fit
that PLL/DLL IP into your design.
With Movellus, it is the opposite. You customize our IP
along as you are designing and finishing the digital parts
of your chip (because it's all digital.) So, we're actually
breaking that trade-off.
Cooley: But if I'm using a True Circuit PLL, I know it works. It's
been tried and it's working. So, with your Movellus stuff...
Mo: Yeah, so does ours. We have silicon working from 130 nm all
the way down to 7 nm.
Cooley: You're telling me you've gotta tweak it (your Movellus PLL),
you've gotta wiggle it (the Movellus PLL) ...
Mo: At design time, yes. It's RTL. It's all digital and
typically nobody asks: "Hey, my adder doesn't work in 7 nm
versus 5 nm???" ... so it's (Movellus PLL) similar PLL
architectures.
Cooley: Okay.
Mo: So there's another important aspect and that is that your
SoC design cycles, especially in advance nodes, are so long.
The PDKs you start with, by the time it's time to tapeout, it
has already changed. You can absorb those changes, into the
digital side very easily -- but what happens to analog?
If you want to be immune to that, then you have to have a
solution like our Movellus PLL/DLL. We have customers that
are working with us because their PDKs is unstable. This
gives us an opportunity.
On the flip side, if you look at the chips, they're very complex
these days, so there's no chip that is single mode anymore.
There's a mission mode, there's a turbo mode, there's a sleep
mode, there's a standby mode, The current M.O. for handling
all those modes is to use your mission mode for IP's and use
it slower for the other modes, and that's inherently inefficient.
So we're giving this freedom to the designer so that they can
actually optimize all the modes without having to worry about
slipping their schedules -- without having to worry about
"this analog is not going to work" or "don't touch my analog."
That's the freedom that we're (Movellus PLL/DLL's) bringing to
the SoC designers and to the architects.
Cooley: My understanding of that was the tweaking is at the design time.
You're saying it's functional tweaking? You can actually do...?
Mo: The tweaking is RTL.
Cooley: Okay, but it's at design time? It's not during operation. You
don't change how the DLL behaves.
Mo: Well, you can always program it in silicon as well. But at
design time you can actually tweak it (Movellus PLLs). If
you end up designing something that is really general purpose,
it's not efficient. It's all about customizing the Movellus PLL
for your application.
Cooley: Tuning it for the one application, okay.
Mo: Yeah.
Cooley: Okay.
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