( ESNUG 593 Item 08 ) ------------------------------------------------------ [05/12/23]
Subject: Anirudh's 9 jabs directed at Synopsys and Ansys from his CDNlive'23 keynote
SANTA CLARA, CA, 03/29/2023, PRnewswire -- Synopsys.ai blah blah AI-driven
blah blah DSO.ai runs on top of Fusion Compiler and IC Compiler II to search
very large PnR solution spaces for optimal results blah blah blah... 25%
less power ... VSO.ai runs on top of VCS for blah blah optimal results...
for 10X faster functional coverage ... TSO.ai runs multiple copies of
TextMAX for enhanced defect coverage, fewer test patterns, and faster time
to results ... blah blah blah
... multiple parallel training runs ... learning ... training ... Synopsys.ai
has 160 tape-outs blah blah blah Renesas, MediaTek, IBM, ST, Samsung, ARM, and
SK Hynix are current users using some part of Synopsys.ai.
- John Cooley's interpretation of the SNUG'23 news from 03/29/2023
From: [ John Cooley of DeepChip.com ]
Hi, DeepChip readers,
Three weeks ago, I flew into the SFO airport for both the Real Intent Users Group 2023
and the CadenceLIVE Silicon Valley 2023 user group meetings.
Because Boston-to-SFO-to-Boston burns 2 full working days for me just for travel -- plus
it seriously messes with my internal sleep clock -- I try to pack as much as possible
into these 6,200 mile Silicon Valley round trips.
Here's what I saw and heard Anirudh say in his CadenceLIVE keynote.
First off, I have to give it four-out-of-four-possible stars for its theatric set up.
Before the speech, you had to walk this long dramatic dark hallway just to get to the
keynote ballroom itself. Once in the ballroom, the lights are kept low even while you're
tyying to figure out where to sit. I instinctively tried to go to the front row because
that's where I can get my best pics of the speech ...
... but the blonde Cadence Hollywood Director Lady with a walkie-talkie on her belt, a
cell phone, an iPad, and a headset on her head -- the four universal power tokens showing
that she is clearly the one in control here -- intercepted me with:
"Oh, John, you do NOT want to be in the front rows because the big screen will
flood you out. You want to sit in the middle for maximium visability.
It's like IMAX. Sit too close and it'll overwhelm you, honey."
As per the Director Lady's instructions, I sat in the center of the audience.
About 20 minutes in, I counted 583 (+/- 4) people seated and 123 (+/- 5) people standing
along the back and side walls.
Making it 706 (+/- 9) total audence members watching Anirudh's keynote.
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SLIDE 1: An Engineering Shortage Blesses Everyone
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WHAT ANIRUDH SAID: Blah, blah, CDNS has 10,000 people, 9000 are engineers or computer
scientists. 60-65% of CDNS is R&D. 25% is customer support. CDNS is 90% engineering.
blah blah our key strength is developing and supporting computational software ... blah
blah ... chips now are 100 billion transistors. 1 inch by 1 inch. By 2030 there will
be 1 trillion transistors on the same size chip. 10X increase in # of transistors. Blah
blah ... complexity to increase over next 7 years ... it's impossible to hire 10X or 20X
more HW engineers -- so Cadence EDA automation has to step up to fill that void ...
WHAT COOLEY HEARD: Chip sizes up 10X in 7 years ... design starts up 4X in 10 years...
your chip house bosses will be furious because they will need to hire 10X to 20X more
engineers -- but that's impossible -- so my 9,000 CDNS engineers will be going ga-ga
trying to fill this hole in engineering body count with a crap load more automation...
blah blah... being a HW engineer over the next 10 years is going to kick ass!
Also, Anirudh's implied message here directed at Wall Street is that overall EDA sales
will explode over the next 10 years because of this crushing HW engineering shortage.
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EDITOR'S NOTE: I have to stop to explain the backstory going on here ...
CONTEXT IS EVERYTHING: Cadence & Synopsys have been bitter Coke vs. Pepsi rivals
over the past 30 years.
The two companies offer simular EDA tools -- with major functional overlap.
And they're both chasing the same EDA Purchase Orders and all of the
same chip and system houses -- in a mostly zero sum game.
When Cadence gains a foothold in Intel, it directly translates into business $$$
that Synopsys has lost -- or will eventually lose. And vice versa. Same with
Apple. And Samsung. And MediaTek. And Broadcom. And Facebook. Etc...
Always, always, ALWAYS keep in mind in this blood feud that:
Everything Cadence says (and does) is to either attack or to defend against
something that Synopsys is doing.
Everything Synopsys says (and does) is to either attack or to defend against
something that Cadence is doing.
WHAT REALLY HAPPENED: Cadence & Synopsys have an almost identical employee base.
Folks regularly jump ship to join the other company. Both companies know that
Machine Learning and Artificial Intelligence are hot buzzword-du-jours in EDA
tool developement; so both companies' R&D are furiously weaving ML/AI into their
existing EDA product lines. Both companies.
Right before the SNUG'23 meeting:
- Anirudh had Cerebrus with AI for PnR and Verisium with AI for verification;
which matched Aart's DSO.ai for PnR and VSO.ai with AI for verification.
- While Anirudh is weak in scan/ATPG test tools, Aart kicks ass in scan/ATPG
test tools. Right before SNUG'23, Aart had TSO.ai -- which is ML/AI for
scan/ATPG -- and Aart rightfully had bragging rights over Anirudh on test.
- But, instead of gloating over their TSO.ai lead, SNPS Marketing crafted
this over-arching Synopsys.ai story that heavily implied that CDNS was
overall super weak in ML/AI -- while was SNPS kicking ass in ML/AI.
- Then Aart pushed Synopsys.ai out at SNUG'23 to Wall St. and Forbes and CNBC
and the investment community -- which is why 2 weeks later Anirudh's
CadenceLive'23 keynote was Anirudh effectively calling BS on Synopsys.ai.
... OK, with this back story now explained, I can now return to dissecting what
Anirudh said plus do a tally of his anti-SNPS and anti-ANSS jabs! - John
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JAB 1: Cerebrus with AI kicks ass!
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WHAT ANIRUDH SAID: Blah, blah, blah a CEO [probably at Broadcom] told me every time his
chips goes down a node [like 16nm down to 10nm, for example] he would get a 15% to 20%
boost ... but process migration costs mucho engineering man-hours, time, and $$$. Go
from 7nm to 5nm, it's only a 10% boost. Blah blah ... stay in the same node and instead
use Cerebrus with its AI stuff gets you that same 10% to 15% -- with far less hassle!
WHAT COOLEY HEARD: My Cadence Cerebrus and its AI improvements kicks ass and more than
beats Aart's lame Synopsys DSO.ai equivalent! We're mature AI PnR. Try it and you
will see Cerebrus gets killer PPA with far less man-hours. My slide data proves it!
[ A lot to unpack here. Here's the Cooley Best Guess analysis going left to right:
- 38% less leakage power multi-core 3nm CPU IP [ most likely ARM ]
- 30% less leakage power 4nm server GPU [ NVidia or Intel ]
- 8% less total power 16nm SoC server block [ Broadcom or ST ]
- 8X less man-hours 5nm GPU [ NVidia or AMD ]
- 10X less man-hours 3nm moble CPU [ Apple or MediaTek ]
- 6X less man-hours 5nm server SoC block [ Facebook or Alibaba ]
- 60% better TNS 7nm automotive SoC block [ Tesla or Renesas ]
- 62% better TNS 3nm moble CPU [ Qualcomm or Apple ]
- 45% better TNS 4nm server SoC block [ Intel or Qualcomm ]
Facebook/Alibaba/Tesla caught my eye the most because they're not the usual semiconductor
logos (like ARM/Apple/MediaTek/NVidia) that CDNS/SNPS/MENT traditionally sells to. ]
This looks like Anirudh is calling bullshit on Aart's earlier Synopsys.ai announcement at
SNUG'23 two weeks prior to CadenceLIVE'23.
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JAB 2: Cerebrus with AI really kicks ass against Synopsys.ai and DSO.ai
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WHAT ANIRUDH SAID: Blah, blah, blah the customer response to Cerebrus with AI has been
tremendous blah blah all our big customers are using Cerebrus blah blah over 180 tapeouts
blah blah we started with implementation, and will be extending up to more architecture
exploration ... TSMC, Global Foundries, Samsung, Intel Foundry all support Cerebrus.
WHAT COOLEY HEARD: Blah, blah, blah this is my F.U. to Aart's 160 bullshit Synopsys.ai
tapeouts that he pulled on me at his SNUG'23 two weeks ago. Aart claims 160 tapeouts
total? Well *my* Cerebrus with AI (his DSO.ai equivantant) has over 180+ tapeouts
alone; and that's not including tapeouts for all my other Cadence AI tools!!!!!
It was NOT a "looks like Anirudh calling BS"; it was unquestionably Anirudh calling BS
on Synopsys.ai ... and the rest of his keynote expands on this theme.
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JAB 3: my new Virtuoso Studio with AI kicks ass!
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WHAT ANIRUDH SAID: Blah, blah Virtuoso has done phenomenally well over the last 30 years
as one of Cadence's franchise products... always wanted more automation in Virtuoso; more
PnR and more productivity for the full custom designer... Blah, blah Virtual Studio adds
ML/AI to Virtuoso and we see 3X full custom layout gains.
Analog Devices, Renesas, Mediatek, TSMC all endorse Virtual Studio. Blah, blah... spoke
to a quantum computing company doing 3nm/2nm design [ probably Microsoft or IBM ] and
they use Virtuoso Studio... blah, blah, you should check out our AI Virtuoso Studio.
WHAT COOLEY HEARD: Blah, blah, we've added ML/AI to our Virtuoso full custom layout and
it kicks ass! Blah, blah... for the bleeding edge full custom nodes (7/5/4/3/2/1nm)
*my* Cadence Virtuoso full custom layout plus ADE both have 95% market share with in
the Tier 1 houses -- something Aart would love to have -- but he doesn't! -- and again,
*my* new Virtuoso Studio has Artificial Intelligence bringing 3X productivity gains!
This was Anirudh gloating over:
1. how his Virtuoso owns 95% market share in the Big Boy Accounts
2. "look, ma, my new layout now has AI!"
3. Synopsys is super weak in full custom/MS compared the Cadence.
and what Anirudh is building up to is telling the world that Cadence owning full custom
paves the way for Cadence dominating in both 3D-IC and then chiplets.
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JAB 4: my new Allegro X AI kicks ass!
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WHAT ANIRUDH SAID: Blah, blah, blah the first thing any mechanical designer talks about
with the electronics of a new system is NOT the chip, but is its chip packaging ... blah
blah ... a modern PCB has thousands of elements on the board ...
... Allegro X and Allegro X AI can do automatic AI magic on those thousands of elements
in hours, instead of days that were required before manually... blah, blah, blah, blah
... examples of "magic" from Schneider and Kioxia. [two very busy PCB pics on screen]
WHAT COOLEY HEARD: Blah, blah, blah... my Cadence Allegro X overall has 80% marketshare
of the chip packaging market -- and it's like 95% for the really challenging designs.
And chip packaging is a critical 3D-IC niche where Aart waaaay behind on. Both Cadence
and Mentor have close to 30 years of chip packaging experience. Synopsys R&D is in
catch up mode here having just started on chip packaging in Q3 2020.
Oh, and now I've launched Allegro X AI, so Aart's even further behind me! Nyah! Nyah!
And he who controls semiconductor chip packaging, controls the chiplets universe!
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JAB 5: my Cadence 3D-IC R&D guys have 28 years of PCB and chip packaging experience!
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WHAT ANIRUDH SAID: Blah, blah... [Mentor Xpedition and Cadence Allegro] are the two big
platforms for PCB and package design and Allegro is one of the big ones. In the old
days people would ask: "what's this packaging stuff?" But that has changed now.
Whether it's the big foundries or the big customers, advanced packaging has become a
forefront technology that they all ask me for.
WHAT COOLEY HEARD: A 2nd sucker punch reminding everyone that SNPS has absolutely zero
in PCB layout, plus a total newbie in chip packaging -- while Cadence has 28 years of R&D
doing exactly this. The history of chip packaging is timelined here -- culminating
with Cadence being the "First AI-driven 3D-IC chiplet and system design solution".
Notice "chiplet", "3D-IC", "AI", and "first". It's a 2nd sucker punch at Synopsys.ai!
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JABS 6 & 7: we're crushing it against Ansys, too!
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WHAT ANIRUDH SAID: Blah, blah... we have more than 1,000 R&D engineers at Cadence working
on these [ Ansys crushing ] physical system design and analysis tools. ... power and
thermal are supercritical now ... whether it's 3D-IC, data centers, electric cars...
... and I'm proud of how my Cadence Voltus/Celsius/Tempus/Innovus/etc. all play nice with
each other. ... physics based simulation ... CFD... Sparse matrix... GPU... Stanford.
WHAT COOLEY HEARD: This is Anirudh doing a 3-way kung fu double kick on Ansys alone along
with the Synopsys-Ansys Fusion Compiler/Redhawk-SC integration.
Anirudh is playing up that you CANNOT do all this physics based work in a Synopsys-only
flow, nor in an Ansys-only flow, nor even with a combined Synopsys-Ansys flow.
Gosh, would it be rude to point out that only Cadence has the complete physical design
toolset going RTL => gates => placed-gates => PnR => power => thermal -- all with the
same internal databases and with integration between the tools and integrated reports?
And didn't Aart himself repeatedly complain about Frankenstein flows years ago?
"Companies already want to deal with fewer vendors. One reason is economic.
The other is technical. The Frankenstein flows will become less and less
productive over time. Our industry is following the same trend as the
IS industry and companies like SAP and Oracle. Customers want a complete
solution."
- Aart de Geus, CEO of Synopsys (SNPS Earnings call for 2Q 2005)
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JAB 8: Optimality is the AI that drives my anti-Ansys tools!
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WHAT ANIRUDH SAID: Blah... Optimality uses same AI algorithms in Cerebrus, but for our
physical system design/analysis tools. [ Celsius/Voltus/Sigrity/Clarity/EMX/Fidelity ]
... reinforcement learning algorithms... dramatic results in CFD in electromagnetics...
Try Optimality. It does AI optimization on top. It can provide a lot of value.
WHAT COOLEY HEARD: my Optimality has all the same Cerebrus AI algorithms but it's now
stuffed into all my anti-Ansys physical 3D-IC and chiplet making tools.
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JAB 9: screw you, Synopsys.ai! -- my Cadence has generative AI everywhere!!!
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WHAT ANIRUDH SAID: We announced 2 major new products. Virtuoso Studio for analog with a
lot of AI, and Allegro X AI for PCB and package design with a lot of AI. Blah, blah ...
now all 5 major Cadence product lines all work under Cadence JedAI, which is the AI that
is on top of the AI that's already in each of my 5 major product lines.
JedAI is data analytics AI to manage your tools (and data) in a multi-run environment.
Blah blah... has open APIs for the customers to work directly with JedAI.
WHAT COOLEY HEARD: Can you believe this bullshit, John??? I had all my slides and
keynote all practiced and ready to go -- just 10 days before CadenceLive, Aart then
pulls this Synopsys.ai crap implying SNPS has flanked CDNS in Artificial Intelligence!
And this Synopsys.ai BS went out to the users, and Wall St. and investors -- everyone!
I had to have my staff go into a mad rush to rejigger my keynote to spam AI, AI, AI on
every possible slide -- just so the world would know that Cadence has tons of AI -- just
exactly like every other damned high tech company in Silicon Valley!!!
I had to drastically cut my talking time about the Cadence wins in Palladium, Protium,
Pegasus, Spectre-X, Innovus, Genus, Tempus, Jasper, Xcellium, Conformal, Modus, and DFM
just to have enough time for the added AI content to counter this Synopsys.ai bullshit!
"I like submarine commanders. They don't have time for bullshit; and neither do I."
- Franklin D. Roosevelt, 32nd U.S. president (1882 - 1945)
"The best defence against bullshit is vigilance. So if you smell something,
say something.
- Jon Stewart, U.S. comedic TV host (1962 - present)
"Welcome to the world of bullshit, my dear. You have arrived."
- Elton John, British singer and pianist (1947 - present)
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