( DAC 01 Item 6 ) ---------------------------------------------- [ 7/31/01 ]
Subject: Iota, Sequence/Sente WattWatcher, Synopsys Power Compiler, Offis
POWER DESIGN: Sente's WattWatcher & Synopsys PrimePower tools focus on
analysis and estimation from your design's RTL code -- and a lot of that
depends on the anticipated behavior of the design. Static power isn't that
hard to figure out. The 'bear' is trying to figure out the *dynamic* power
that a chip uses -- and that can be all over the map! The big question,
then, are how accurate are these estimates? WattWatcher has owned this
market for years, but it appears that PrimePower might be snapping at their
heels. Iota and Offis sell power planners. Controversial because people
are used to doing this by hand. Synopsys Power Compiler is the only tool on
the market that tries to re-optimize your design to consume less power.
"The Offis Orinoco guys had some neat ideas about going from C/C++ down
to gates optimizing for power. However, without an underlying logic
synthesis engine, I would never trust Orinoco to give me real results.
The idea of generating scripts to coerce Behavioral Compiler into
giving them the schedule that they thought was optimal (for power) was
ridiculous -- not ridiculous in theory, but in practice."
- [ An Anon Engineer ]
"Offis:
Orinoco is an algorithmic and RTL level power estimation tool. If
you're at the algorithmic level, you need to give it some hints about
the number of pipeline stages. You make a library of power for each
cell using Synopsys Designpower or Powermill, then abstract this to
get power estimates for RTL blocks. They said they are within 20% of
actual power but then added a ton of provisos and eventually said they
were better at comparing two different designs. Actual power is
highly dependent on both instruction and data so this is a more
reasonable claim.
Iota also does gate level IR drop analysis. It characterizes your
technology to get speed and IR drop. They say they're as accurate as
Railmill but much faster since it's gate level. They can also modify
the SDF for your design to account for the instance specific voltage."
- John Weiland, Intrinsix
"IOTA Technology has a very nice gate-level IR drop map across the
chip. Provides a Chipviewer."
- Raj Sayana of MoSys
"Another technology that caught my attention was from IOTA technologies.
They have power planning tools that help one to plan and implement
power planning structures easily into the chip, starting at an early
stage in the design cycle. They analyze the design/block and give
quick feedback of the IR drop with every little tweak."
- Nagendra Cherukupalli, Cypress Semiconductor
"I think that Iota's PowerPlanner tool has a very useful role to play in
early (pre-gate) chip power planning. It strongly complements the
Simplex VoltageStorm tools, which kick in after gate-level netlists
are available."
- Mike Carter of Mosaid Technologies
"I stopped by to talk to the Iota folks. What they show is something
really cool missing from our flow. I talked to our APR guys about it
and they said that they had already done an eval of the tool several
months ago and that it did not live up to expectations. So,
unfortunately this falls into the "cool but really smoke, mirrors, and
glitz on an ideal test case" software-- which is unfortunate."
- [ An Anon Engineer ]
"If you're designing a chip for a portable device, I've heard good
things about Power Compiler, although I haven't used it myself. But
if you don't care about power, you don't need it."
- Oren Rubinstein of Nvidia
"We looked at both Power Compiler and the power capabilities within
PKS. While I think that Cadence has a more elegant solution for power
reduction during synthesis and a more tightly linked solution for
physical/functional synthesis, I believe that the dominance of the
synthesis market will hinge on who gets the design starts first and
with those starts the support of the ASIC manufacturers. Synopsys
has that momentum."
- Richard Lowry of Starburst Technologies
"We did have Power Compiler, but simply did not use it as we were too
busy meeting our area and timing goals. Perhaps for battery-powered
devices, they have more use, but not in our environment."
- [ An Anon Engineer ]
"We used Power Compiler on our last ultra low power design and the
estimated gate-level power numbers were very close to our measured
silicon values. We like the tool and will continue to use it. You
need to work with your library vendor, though, to ensure accurate power
tables are in the .lib files otherwise your numbers are meaningless."
- [ An Anon Engineer ]
"We may use Synopsys Power Compiler this year. I think the Sente tools
are generally pretty good but I don't use them in my current job."
- Carl Wakeland, Creative Advanced Technology Center
"Power analysis was also listed in this category. We are definitely
interested in Sequence/Sente and Synopsys tools, and are likely to
evaluate both in the next few months. My impression is that Synopsys
has a more comprehensive (and expensive) solution with Power Compiler.
My understanding is that PrimePower will have full RTL analysis in the
next release but that Sequence has it now, along w/ good lib support."
- [ An Anon Engineer ]
"We've been looking at Power Compiler for some future designs but
nothing at the moment."
- Phil Hoppes, Intersil
"We will probably dump WattWatcher for PrimePower."
- [ An Anon Engineer ]
"We have used Wattwatcher from Sequence (previously from Sente) for a
while. It does a decent job of vector-based power calculations.
Unfortunately the price is very high, so we have just started an
evaluation of PrimePower."
- [ An Anon Engineer ]
"We have used the Sequence WattWatcher power analysis tool. It works
quite well (within 10-15% at the RTL level) as long as your ASIC vendor
supports it by providing the power libraries."
- [ An Anon Engineer ]
"RTL estimators - Sequence (Sente) WattWatcher:
Strengths
- excellent visualisation features (colorised display of hotspots)
- crossprobing to RTL
- can be Tcl-scripted
Weaknesses
- multiple clock domains must have their activity factors
(manually) referred to some base frequency
- pseudosynthesis technique is fast but regularly produces
funny/bizarre results
- probabilistic estimation should default more intelligently
- Synopsys (SAIF) and Sequence(Sente) have different PLIs, that
I would like to see these unified. Adding Linux support for
both will be essential for capture from real-world simulations.
Good tool, let's see proper multifrequency support and Linux port."
- [ An Anon Engineer ]
"We once tried Sente and it looks quite reasonable. But I have no clue
how good it matches the real silicon."
- [ An Anon Engineer ]
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