( DAC 01 Item 13 ) --------------------------------------------- [ 7/31/01 ]
Subject: Cadence NC-Verilog, Synopsys VCS, Model Tech, Synopsys Scirocco
SAME OLD, SAME OLD: If you take a look at last year's DAC Trip Report,
you'll find that Cadence NC-Verilog & Synopsys VCS were fighting neck and
neck; Model Tech were doing really well in the VHDL and Verilog/VHDL
co-simulation market; and nobody was very impressed with Synopsys Scirocco.
Not much has changed since then except a few more people were talking about
using Cadence NC-SIM instead of ModelTech for Verilog/VHDL co-simulation.
Oh, yea, and some people commented that they liked the C and Vera portals
that VCS has. Plus quite a few people eagerly want VCS and NC-Verilog to
quickly adopt the Verilog-2000 initiative (but I put those comments in the
Superlog/ Verilog-2000 part of this report.)
"Synopsys VCS:
Don't know about NC Verilog. We use VCS here. It usually works fine
but I've noticed strange behavior in the past with gate level netlists.
VCS saw signal changes where there were none. I double checked the
netlist at that time and resimulated with Verlog-XL which gave me
correct results.
Synopsys Scirocco:
Scirocco is okay. So far the cycle mode has not been usefull since
too many language constructs are not supported for cycle mode.
Synopsys really has to work on this. We also had some problems with
VirSim/Scirocco where Virsim displayed signals incorrectly. Scirocco
2000.12 seems unreliable and we stopped using it after a while.
Mixed HDL:
We use VCS and Scirocco. This works okay except that you get race
conditions between clock and data on the Verilog/VHDL boundary.
- Menno Spijker, Mitel Semiconductor
"We had too many problems with Scirocco and have moved mostly to
Modeltech with NC-Sim for high speed mixed mode simulations."
- [ An Anon Engineer ]
"With NC-Sim we have the advantage of mixed language simulations (which
Synopsys says they have it too; but to be honest I am yet to see anyone
using VSS/Scirocco.)
Fintronic, SimuCAD, and Aldec are all low cost alternatives. Aldec
is more promising though."
- [ An Anon Engineer ]
"I like Synopsys VCS DirectC interface. The biggest problem I see in
Verilog is the lack of signed reg's, so the synthesizers keep
everything as unsigned and signed arithmetic has to be dealt on case
by case basis. It would be nice to have the signed regs for datapath
(the signed representation would have to be specified as well somehow).
I hope Superlog will gain some momentum."
- [ An Anon Engineer ]
"VCS and NC-Verilog run head-to-head. We prefer the VCS viewer vs.
Signalscan. Overall we prefer NC-Verilog (cost performance). NC-SIM
is in use quite happily. Interested in Verilog 2000."
- [ An Anon Engineer ]
"I use VCS for simple chip-level and board-level simulation. The
incremental compile option is handy, and we run on both SOLARIS and
Linux platforms. We use our own internal cycle-based simulator for
system simulation because of performance and data volume."
- Roger Bethard, Cray Computers
"VCS 6.0 especially with the following switches (+rad, +applylearn,
+nbaopt, +notiming) is really much faster. Unfortunately you still
have to use Vera for reentrant tasks, and there is still no support
for always@(*). Both of these are in the Verilog-2000 standard
and should be put into VCS."
- Dan Joyce, Compaq Computers
"Did a Verilog simulator benchmark around March'01. Design was a
synthesizable, RTL-level core 500 K gates, and a behavioral testbench
around it with ~2000 lines of code. The simulators were:
Verilog-XL v2.8 (yeah, a bit old)
Modelsim v5.4d (current version is 5.5c)
VCS v5.2 (current version is 6.0)
NC Verilog v3.11 (current version is ???)
Here are the results for normal runs and with optimizations on:
Simulator | Memory(MB) | Compile (sec) | Simulate (sec) | Total (sec)
---------------------------------------------------------------------
Verilog-XL| 97 | - | 2710 | 2710
+turbo+3| 84 | - | 1580 | 1580
Modelsim | 28 | 28 | 473 | 501
-fast | 24 | 40 | 427 | 467
VCS | 6 | 10 | 43 | 53
+rad+2 | 6 | 27 | 43 | 70
NC Verilog| 19 | 12 | 18 | 30
As one can see, VCS and NC are compiling to machine code. VCS uses
less memory, but is a factor 2 slower. This might have changed a bit
with the new version.
Modelsim compiles to machine-independent, intermediate code, which is
then interpreted. Think of Java. Still a factor 10 behind NC and VCS.
But it has a complete set of GUIs (waveform, etc.), which is nice for
debugging.
My recommendation: Modelsim is fine for small to medium designs, since
it's easy to handle and doesn't need additional debugging tools. But
for large designs, VCS or NC are a must, due to their superior speed."
- [ An Anon Engineer ]
"We use VCS, and want to experiment with the Linux version."
- Paul Schnizlein, Agere Systems
"So far we've only tried NC Verilog and VCS. VCS is faster and runs
on our Linux boxes very well indeed. Too bad Verilog has enough
flexibility in order of execution to make it a little problematic
moving from one simulator to another. Still VCS will probably does
pretty well here."
- John Szetela of AMD
"It looks like a dead heat btw NC and VCS. VCS might have a slight
lead still, but they're in the same general range. Which is good
for us customers. Competition is a good thing."
- Paul Zimmer of Cisco Systems
"I was impressed with the number of Verilog-2001 features that have
already been implemented by the ModelSim team. I think by December
2001, many of the Verilog-2001 features will be mainstream and safe
to use across multiple vendors."
- Cliff Cummings of Sunburst Designs
"For simulators I can now compare ModelTech vs. NC-Sim and in my opinion
ModelTech is the better choice -- particularly the waveform, the
hierarchy browser not to forget the dataflow window which lacks in
NC-Sim completely."
- [ An Anon Engineer ]
"We use both VCS and NC-Verilog. Their differences are minor. You
can drive yourself nuts trying to see which is the best since they
seem to leap frog each other. I see you get more with VCS if you
use Vera."
- Phil Kuglin, Credence Systems Corp.
"We use VCS, NC, and XL. For debugging, nothing beats the completeness
of XL warning messages."
- Luis Basto, Analog Devices
"Speed-wise, I believe that NC is evenly matched with VCS. However,
NC's mixed-language capabilites are a winner in today's IP re-use
world. The latest version has improved code coverage features, too.
Synopsys never had good VHDL simulation support. Modelsim maybe has
a slight edge on the mixed-language stuff, but it is much slower.
Aldec could break in to this market, especially if their Riviera IPT
PCI cards work as well as they say."
- Andrew MacCormack, Tality/Cadence
"We use both. The last purchase was NC-Verilog because VCS did not like
to use poking all the registers in the chip with the PLI. They have
said they fixed this in VCS 6.2, but I have not had time to test it
out. VCS is easier to compile and use. I suprized both Cadence and
Synopsys by telling them that it was faster to do a full re-compile to
a locally installed disk than it was to do an incremental compile over
NFS. Has anyone else seen this?"
- [ An Anon Engineer ]
"I did the performance comparision between VCS & NC-Verilog 3 years ago.
VCS owns better performance. But I found a problem on VCS last year.
From our observation, NC-Verilog works correctly while timing
delay/check exist negative value in the SDF. The VCS's behavior is
weird (its simulation results are incorrect.) Even the Synopsys's
consultant in Taiwan can't help me solve it! It force me to replace
all negative valuse as zero in SDF file. VCS behavior is then normal."
- Jeong-Fa Sheu of Acute Communications
"No change. I still like VCS."
- Kris Monsen of Mobilygen Corp.
"NC-Verilog seems better than VCS but it still is having issues with
integrating PLIs."
- Rick Price of Ensemble
"I have been a big fan of VCS for many years and have seen about a 4X
speedup over XL during that time. Now I have converted to NC-Verilog
and with LDV3.1 and later. I have been very impressed with it. I see
about a 6.5X speedup over XL and the ease of use is quite good. The
ncbrowse tool is handy as well for spotting errors as the log file can
be quite large and the messages are spread out."
- David Hollinbeck, LTX
"VCS and NC-Verilog both rock. MTI is a Piece Of S---. Debussy
is a must have."
- Sean Smith, Cisco Systems
"We use Modeltech pretty much exclusively here, just because of its
capability to simulate the mixed language designs. These days,
extensive use of third party IP is used in virtually every chip. One
cannot dictate to the third party company to use VHDL or Verilog only.
This gives rise to mixed language RTL, thus our need for MTI's mixed
language simulator."
- Himanshu Bhatnagar of Conexant
"We use Modeltech for VHDL/co-simulation and VCS for all-Verilog
designs. I evaluated Synopsys Scirocco and was not very impressed.
I am a long-time Modeltech user, and found the Scirocco TCL
implementation to be weak and buggy in comparison to Modeltech's
fully integrated TCL interpreter. Also, the Scirocco simulator had
a crash rate above my pain threshold."
- Carl Wakeland, Creative Advanced Technology Center
"Modelsim 5.5b
1) New hierarchy browser built into the main window that
has a couple of modes to use it both before and after
code loading. Can use to grab and load code. Can use
it to look at compiled libraries. Can use it to traverse
loaded code.
2) Code coverage (in SE mode only). Line coverage only.
Interactive, can hop to uncovered lines.
3) Performance (in SE mode only). Shows post-sim results
and can interactively hop to bad code sections, fix
em, rerun and get new results.
4) Wave compare: Can load in an old wave file and interactively
or in post process, graphically compare the results. Can set
tolerances to get rid of phony miscompares."
- Peet James, Qualis Design
"NC-VHDL is a lifesaver for us! We do all our RTL simulation using
Modelsim in VHDL. Then, we run the gate-level sims in NC-VHDL.
Modelsim 5.4 just could not cope with multi-million gate netlists and
SDF. We have not benchmarked Modelsim 5.5, which claims to be better.
Why doesn't Mentor support Modelsim PE on Linux?"
- [ An Anon Engineer ]
"Over the years, I've gone from Daisy, to Mentor, to Mentor Framework,
to ModelTech, to Synopsys VCS, to Cadence Leapfrog, to Cadence
NC Verilog, back to ModelTech, and now back to VCS. (There was a
switch from schematic simulations, to VHDL, to Verilog somewhere in
there.)
Personally, the easiest tool to understand compilation was ModelTech,
particularly when they did mixed VHDL/Verilog. Compiling EVERYTHING
into a single library that you could easily find just made sense. It
just ends up that a simulator is a simulator. The most important
issue is which tool your Fab Vendor will allow for Golden Simulations;
after that it comes down to speed."
- Gzim Derti, Improv Systems
"We currently use Cadence NC-Verilog. Our benchmarks showed NC to be
about half as fast as VCS on RTL simlations and about twice as fast
on gate level simulations. Both VCS and NC are good simulators and
any benchmark tends to be very "space/time continuium" oriented.
Depends on what and when you did it. Cadence and Synopsys work pretty
hard to keep these packages competitive. Biggest plus here for users
is Linux versions which can run on Intel platforms. Taking cost and
performance into mind we find we get from between a 6x to a 10x
improvement over Sun hardware."
- Phil Hoppes, Intersil
"Primarily we use Model Technology's ModelSim. It works quite well with
mixed VHDL and Verilog, and we like the user environment. Also, I have
had much better luck using it with multiple third party tools (e.g.
code coverage) through ModelSim's VHDL "C" interface. My benchmarks
indicate about 2x performance for VHDL using Cadence NC-VHDL over
ModelSim, neglecting the effect of BFM's and such, so I would not
dismiss NC-SIM. I cannot comment on VCS and other simulators."
- [ An Anon Engineer ]
"Synopsys VCS is still going strong. We have both at Nortel but I
haven't found a reason to switch simulator yet. I have seen up to
50% speed up with two-state simulations which is very encouraging."
- Anders Nordstrom of Nortel
"My data is getting kind of dated, but it is still my opinion that
Cadence NC-Verilog outperforms Synopsys VCS. I also have a bias
against using any Synopsys tool because of their price and
licensing policies.
I have used Modeltech off and on for the last year and a half. I
think I still prefer the NC-Verilog/Signalscan environment over the
MTI environment but MTI is more reasonably priced, is pretty fast,
and probably has a little faster learning curve. But Cadence has
been working on the ease of use of the NC tools and they are much
easier now to get started with than they used to be. I think the
newly added waveform compare functionality is stupid, but apparently
a lot of users want that type of thing."
- Tom Loftus, Intrinsix
"We're still using Modelsim exclusively. We like the ease with which
it handles mixed Verilog-VHDL simulation, and that it runs on all the
platforms we have: Sun, Windows, and Linux."
- John Lynch of Pixelworks
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