( DAC 04 Item 21 ) --------------------------------------------- [ 02/09/05 ]
Subject: Sequence PowerTheater vs. Synopsys Power Compiler
A HOT MARKET -- If you have a tool that can cool a chip down, you're in the
right place at the right time because the whole design world will beat a
path to your door. (There's a reason why Magma is stressing its low power
flow in its advertising campaigns.) At the RTL level, the two big boys in
power opto are Sequence PowerTheater vs. Synopsys Power Compiler.
PowerTheater Pros:
1) We mainly use PowerTheater for RTL power estimation and have seen
good correlation against gate-level. Whereas the Power Compiler
RTL flow is only good for relative accuracy.
2) Pretty fast and same type of setup for RTL and gate-level of
the design.
PowerTheater Cons:
1) Longer setup time.
2) Capacity issues with gate-level analysis. PrimePower handles
gate-level analysis better and faster. We also use PrimePower
for gate-level.
We like PowerTheater for the purpose we are using it for.
- Rajiv Saini of Freescale Semiconductors
I'm not a hands-on PrimePower nor Power Compiler user. I can talk
about PowerTheater by its own though.
1. PowerTheater does analysis based on the RTL design. Can be done
at the early stage of the design. So, it gives hierarchical power
analysis from the chip top down to leaf cells.
2. PowerTheater has fairly good correlation between RTL and gate-level
results for a structural design, less than 20%. But not as good if
the design is behavioral.
3. The more itemized the design is, the better job PowerTheater does
the analysis.
4. It does good job tracing the clock tree and clock gates if there
are any in the design. But clock tree insertion based on the leaf
register counts doesn't have good correlation with gate level clock
tree, which is reasonable.
5. RTL analysis runs quickly for big designs.
PowerTheater itself is easy to learn. Has user-friendly interface.
- Kai Chirca of Texas Instruments
I've been using PowerTheater for about 2 years now. At the time, I
evaluated several other RTL power analysis tools. Power Compiler from
Synopsys and PowerPlanner from Synplicity (Iota?). My design group
is mainly concerned with getting early estimates of power from both
RTL and gates, not necessarily to squeeze out every drop of power out
of the design.
Without a doubt, PowerTheater won hands down. It's fairly easy to use,
pretty intuitive for the most part and pretty stable on bugs. They did
come out with a release that broke with dual power supply libraries,
but Sequence fixed that in a few days.
Sequence has had quite a bit of turn over in their support staff. I've
had 4 AEs in that 2 year period. But as I said the tool is fairly
stable so I haven't needed too much support.
PowerTheater has a very nice user interface or batch mode is also
available. One of the problems is that the GUI doesn't offer all of
the options that are available in the batch, but that seems to be a
very common problem with most tools I've worked with. Not a problem
if you don't use the GUI, but in some of the analysis, the GUI is very
nice to have. You can run the simulation in the batch mode, then
analyze in the GUI.
In terms of performance, I compared the reported power numbers for
RTL/gates in the analysis tools to extracted netlists running PowerMill.
As you might suspect, PowerMill is not a viable alternative for power
estimation over a couple of thousand gates. With very fast run times
(20 min for a 500 k gate design) we are able to get to about 20% of the
real power using RTL. With some tweaking to the PowerTheater setup,
even better. With gates, we are seeing <10% compared to silicon.
Gates do take somewhat longer, reading large VCD files takes a long
time, but PowerTheater has a Verilog PLI that generates compressed
activity files that take much less time to read. It also has a variety
of analysis tools: Power reduction wizzards, vector analysis wizards,
peak and average power analysis.
PowerTheater Strengths:
- fast
- easy to use
- nice GUI
- accurate RTL power estimation (vector or statistical)
- accurate gate power estimation.
- reads Liberty file format with power numbers
- stable in terms of bugs.
PowerTheater Weaknesses:
- GUI doesn't give all same functionality as batch mode
- slows down considerably reading in large VCD files
- high support turnover.
Bottom line is that I am very satisfied with PowerTheater. I've found
it a very productivity enhancing tool and I would buy it again.
- Jon Watkins of Dallas Semiconductors
PowerTheater
Pros: Has RTL power estimation and power optimization capabilities
which are not available elsewhere. Detailed clock power analysis
available and friendly reporting structure.
Cons: FSDB sometimes doesn't work as consistently as VCD. Some
options can be used in batch mode only and not GUI and vice versa
which will need user to switch back and forth between the GUI
and batch modes.
- Deepa Singh of Texas Instruments
We use PowerTheater mainly as an estimator for power dissipation based
on RTL code, whereas our gate-level analysis is carried out by
PrimePower and some in-house tools. Power Compiler is used by some
groups here to do clock gating; we haven't really had much success
doing actual logic optimization for power with it. It's been a while,
and it might deserve a second try.
Anyway, PowerTheater... For our intended use (RTL power estimation) it
is an extremely versatile tool, very, very easy to set up and use...
Some groups within Freescale (i.e., the wireless core and platform
group) have incorporated it into their regular flow, due to its ease of
use and its good (or I should say, fairly good) correlation with
gate-level results.
- David Yatim of Freescale Semiconductors
We will be presenting a paper on our use of Sequence's PowerTheater to
estimate dynamic power for our WLAN chips in SNUG'05.
We used it PowerTheater only to estimate the dynamic power consumption.
We did not use the feature of PowerTheater which points out potential
problems with power since we had to manually check clock gating quite
a bit based on data flow.
I have tried to summarize PowerTheater's strengths below:
- It is fairly easy to setup and use
- Simple to understand and use
- It does what it is supposed to do quite well
- It takes both VCD/FSDB vectors and generates the activity files
- The tool lend itself to be easily automatable (Makefiles, scripts)
- All the data is ASCII data (in various formats) and hence it is easy
to debug the PowerTheater reports if the user sees some anomalies.
- Good tech/customer/field support
Some gotchas in the PowerTheater flow:
- for arithmetic circuits (based on how you code your multiplier in
Verilog), you may get different power numbers.
- Some of their newer versions of the analysis engines generated
different power numbers (differing to a worrying extent) for the
same RTL and same vector set. So, once you are comfortable with
a version of the tool (through some correlation studies), I would
use that as a benchmark before migrating to another version.
When we started looking for tools in the market for power analysis, we
did not find any other tool that would estimate power at the RTL level.
PowerTheater can estimate power at RTL, gates, mixed mode, black box
levels. PrimePower used to be able to estimate power only at the gate
level. We did not use Power Compiler to measure power at the RTL level
(and the flow for PowerCompiler to estimate power at the RTL level is
not as straightforward as PowerTheater)
Most 'power estimation' tools use a VCD file which is 'representative'
of the real world scenario for a very short simulation interval.
PowerTheater has the capacity to analyze really long vector sets
(packets over several 100 us, for example) without excessive
compute/memory requirements. However, the run times can be long.
The RTL estimation of clock tree power by PowerTheater was a
reasonable indication of what the clock tree power should be.
In one of the chips, we found that the power estimate was within 10%
of silicon. This was not just RTL estimation. We used a combinated
RTL data + gate level clock approach to estimate power to get to
these accuracy levels.
Apart from long run times (a 2GB FSDB file could take >24 hrs on a
Linux box) and lack of 64-bit support (which might be in beta now)
I would not say that there are any appreciable weaknesses.
An important aspect of power estimation is the quality of the vectors.
This is where one can be misguided about power if improper vectors are
chosen. Since PowerTheater allows us to use long vector sets, we were
able to estimate average power over several packets -- which helps if
you are not clean on what vectors to choose. Sometimes, it helps to
run PowerTheater for all the modes independently to ensure the 'power'
behavior of the chip. We did find clock gating issues in RTL by
running PowerTheater.
The paper in SNUG'05 goes over the methdology that we used to estimate
power. Overall, we have been very pleased with the results of
PowerTheater.
- Subbu Meiyappan of Airgo Networks
PowerTheater is the "silver bullet" for all my low-power prayers. :)
Ok.... back to reality...
PowerTheater Strengths:
- Only tool that estimates power at the RTL
- It also does a pretty good job estimating power at the RTL.
- Accuracy is within 20% of postlayout power estimation.
- Power Compiler could be "tricked" into doing this, but it
requires developing a methodology such as synthesizing the
clock tree after synthesizing the circuit and then estimating
for power.
Their user support is one of the best I have experienced.
Weakness:
Not a mature tool, there are several bugs. Although the bugs have
been decreasing rapidly over the past year, they are still there.
I think it will be a while until PowerTheater is a robust tool like
Power Compiler or PrimePower. There are also several "segmentation
faults", indicating that the code is not scrutinized/reviewed
before release. This inspires less confidence in PowerTheater by
the users.
PowerTheater claims that it has a set of "wattbots", suggestions that
it detects in the RTL to reduce power. However, I have never seen an
RTL where we could use any of these "wattbots" in our design. I think
this somewhat misleads the users, who choose to run it to improve
their RTL.
I feel Sequence must seriously try to improve their "wattbots" in the
near future (preferable) or not advertise it as feature. This
"feature" currently does not add any value to the user, and may
actually end up discrediting the part of the tool that does power
estimation.
- Aurobindo Dasgupta of Intel
I have used Sequence PowerTheater. It's a nice tool to design power-
efficient designs. The GUI helps one to quickly load the design and
estimate the power at the RTL or the gate-level. It tells a designer
what places power can be saved.
- Gaurav Singh of Virginia Tech
Sequence design sells PowerTheater, which includes the old Sente RTL
power tools that help with vectorless power estimation at the RTL level
and do tradeoffs. New this year is gate level power simulation,
competing against Synopsys PrimePower. They claim their CoolTime is
the first one to simultaneously work on power, instantaneous voltage
drop, timing and signal integrity. All of these require analysis of
nearly identical information but historically the analysis has been
done by different tools. Sequence is working on a tool to insert
switch cells to turn off power to unused portions of your circuit.
Golden Gate Technology, which is teamed with Sequence in some areas,
has a clock tree insertion tool aimed specifically at low power (since
the clock tree is where a lot of the power is dissipated. They also
have a placer that minimizes clock distribution; they claim 3X to 10X
less power but say the clock tree still meets skew and speed easily.
ChipVision sells Orinoco, a tool for RTL and algorithmic power analysis.
Like some of the design planning tools, it first creates a library of
big RTL building blocks with power characterized from a Synopsys .lib
file, then reads the activity data from C or SystemC simulation. They
help minimize power via algorithmic optimization and also by placing
tightly coupled blocks close together.
- John Weiland of Intrinsix Corp.
I am only familiar with Power Compiler. Having a separate point tool
for this job seems rather pointless.
- [ An Anon Engineer ]
Both Power Compiler and Cadence Get2chip equivalent do a good job
(usually) of inserting clock gating. One drawback is that the
front-end tools aren't aware of physical register placement, which
should influence clock gate clustering.
- John Busco of Nvidia
Don't have any of these tools but would look at Synopsys first since
it might integrate smoother with our existing Synopsys tools.
- [ An Anon Engineer ]
We use both Power Compiler and PrimePower. The tools correlate fairly
closely to our silicon results.
- Robert Cram of Gennum Corp.
Have seen some good results using Power Compiler with PhysOpt.
- [ An Anon Engineer ]
We are using Synopsys Power Compiler and found that it does reduce
overall power between 15-30%.
- [ An Anon Engineer ]
Synopsys PrimePower I use.
- [ An Anon Engineer ]
We use the static vectorless in Synopsys PrimePower on all of our
designs. The numbers predicted by PrimePower (on 0.13 um technology)
came to within 20% of the silicon measurments. We use PrimePower to
drive package selection, and to some extent, the IR drop analysis.
- Himanshu Bhatnagar of Conexant
PrimePower is OK.
- [ An Anon Engineer ]
We use Power Compiler, and though it does the job, I'd like to see more
capabilities in controlling it.
- [ An Anon Engineer ]
I haven't run into a power design tool yet which does anything more
than run an accurate simulation of the conditions that you give it.
Coming up with the worst case in an ASIC environment where you have
no control over the placement of the gates is an intractable problem.
- [ An Anon Engineer ]
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