( DAC 10 Item 2 ) ---------------------------------------------- [ 09/02/10 ]
Subject: Solido Variation Designer, MunEDA WiCked
FULL CUSTOM ADD-ON: The company that ranked the second most user interest
at DAC'10 was Solido, which sells a set of fancy schmancy variation tools
for custom design. (Insert other custom buzzwords here.) Oddly enough,
the Munich-based MunEDA, which has been in this niche for close to 10 years
now, barely even got lip service from most users compared to Solido.
"What were the 3 or 4 most INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?"
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The most interesting tool that I saw at DAC was Solido Design's toolset
for variation analysis. Although it's not groundbreaking technology, the
GUI and scripts behind the scenes can help designers do faster variation
analysis than traditionally letting the simulator do it. Plus the
proximity analysis is a unique feature for assisting in deep submicron
layout.
I also looked at MunEDA's toolset but did not get the same vibe from
them.
- [ An Anon Engineer ]
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Solido Design Automation sells tools that run the user's SPICE simulator
(HSPICE, Spectre, etc.). One tool does intelligent Monte Carlo
simulations, the other analyzes things like well proximity to determine
the proper parameters (spacing, etc.) to meet requirements. They say the
tools are integrated into Cadence, Synopsys, Mentor and Berkeley Design
environments and are part of the TSMC 28nm reference flow. New for this
year is a PVT package.
MunEDA (formerly sold by ChipMD) sells a set of tools called WiCkeD
(Worst Case Distance) for optimization of analog parts. The input is
your PDK (for statistical variation), SPICE netlist, testbench, and
desired range of values for critical parameters. It does Monte Carlo
simulations and outputs a sized netlist (i.e. netlist-to-sized-netlist).
They say most competitors do only global optimization and can't optimize
well for yield. MunEDA claims to have better algorithms and supports
Response Surface Modeling (RSM), which they say adds physical effects
like temperature dependence to system level models.
MunEDA is integrated into Cadence Virtuoso, Synopsys Customer Designer
and Mentor flows plus the TSMC RF design flow.
- John Weiland of Abraxas Corp.
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So far my group is not a user of Solido's solution, but I've been
investigating them for 3 years now. I think that their approach could
overcome the biggest issue I see so far deploying analog circuit
optimization tools (e.g. MunEDA et. al.), which is the complexity of
the use model and the "automatic" approach.
To me, Solido is targeting more towards assisting the analog designer
in a GUI driven use model. On the other hand, Cadence is starting to
compete with their enhancements to ADE GXL.
- [ An Anon Engineer ]
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Wicked is a tool provided by a company called MunEDA. Wicked is an
interactive design environment for the analysis, characterization, and
verification of analog circuits. You can run sensitivity analyses
and optimize your circuit to fit the specifications that are set by
your application team.
- [ An Anon Engineer ]
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I attended Solido's Variation Designer DAC demo. Solido is integrated
with Spectre, HSPICE and BDA simulators, as well as Cadence Virtuoso 6.
In the demo I saw, Solido showed how to use its Variation Designer in a
Cadence Virtuoso environment to analyze a custom IC design across
different variation effects (corners, random, environmental and Well
proximity). It then figures out device sensitivities to variation based
on the impact on design specs and recommends specific transistor
modifications to fix/optimize the design.
Solido claimed a 5x-10x speed-up over just using Cadence Spectre's Monte
Carlo analysis. They use a different sampling algorithm and simulation
batching to improve the speed while maintaining the same SPICE-accuracy
by using Spectre in-the-loop.
Additionally, Solido showed some production circuit examples where their
tool was used. In one case, they claimed a 30% performance improvement
due to less guardbanding.
Our company plans to evaluate Solido's Variation Designer, mostly based
on its improved speed and design insight additions on top of Cadence
Virtuoso and Spectre. The fact that this is in Open Access makes its
integration into our design flow particularly advantageous. We also
liked the fact that they were in the new TSMC AMS Reference flow and
that they can handle a wide breadth of custom IC circuits such as
analog, RF, memory, high speed I/O and std cell digital lib designs.
- [ An Anon Engineer ]
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Solido Variation Designer DAC demo
Solido Variation Designer is a transistor level circuit analysis tool
that performs worst case and statistical variation analysis. It is not
a circuit simulator like HSPICE (or Eldo, Spectre, etc) but sets up the
input for the circuit simulators and more importantly, analyzes the
output results to help you fix your design.
Solido addresses variability, which is increasing due to random dopant
fluctuation (RDF), line edge roughness (LER) and poly gate granularity
(PGG) contributions to threshold variation. This leads to larger
variations in circuit performance (delay, power, noise margin) which
ultimately affects your design margin and yield. The problem gets worse
at each successive node, especially at/below 90 nm.
1. Worst Case Analysis - PVT Corner. Variation Designer uses 'Design
of Experiment' (DOE) techniques, and systematically iterates
successive simulations to identify performance and yield
sensitivities in your design. You can use the results to optimize
your circuit.
I have performed circuit optimization using 2-way factorial, a common
(and "simple") DOE technique, so I can attest first-hand to how
laborious this can be. I had to use Excel to set up the input
combinations, feed them into HSPICE, then feed the HSPICE output back
to my spreadsheet to examine the sensitivities to determine the next
set of combinations. Then I repeated the entire process. I could
have scripted it in Perl, but it's time consuming to develop scripts,
plus I was limited to a few input parameters. Solido does this all
automatically with more sophisticated DOE techniques.
2. Monte Carlo - Statistical analysis. HSPICE, Eldo, Spectre all have
MC capabilities, but you still need to analyze the results. Solido
Variation Designer takes care of this by calculating the appropriate
confidence interval (error bars); this directly relates to the
number of samples you take (i.e. the number of sim sweeps you run).
Solido says it has and additional sampling method which has the same
accuracy as conventional Monte Carlo but is faster using their own
optimal sampling techniques.
3. Solido's High Sigma feature is their most intriguing feature and is
currently in beta. Because high sigma circuits require a very high
parametric yield. An example is for an SRAM bitcell. Depending on
the size of the memory and its yield requirement, conventional Monte
Carlo may be impractical to impossible to run. e.g., You must take
10^7 samples to detect the first failure for a 1Mb array with a
yield of 90%. For 99% yield, you must take at least 10^8 samples.
Variance reduction techniques using Quasi Monte Carlo, Importance
Sampling, Bootstrap Re-sampling and other arcane sounding methods
are being used in different fields of study. High Sigma circuit
yield falls under "probability of rare events".
Solido uses Importance Sampling, which involves biasing the input
sampling to areas where those rare failures occur, then weights the
results to account for this bias. The trick is to create a new
input sampling function that increases the frequency of failures
but doesn't have exceedingly small weights. You can reduce the
required number of samples dramatically (many orders of magnitude)
if you hit that sweet spot. If you don't, you can potentially
increase it.
Increasing the number of your input variables complicates using
statistical techniques. Some VLSI literature describes using these
techniques, but they only use a few variables, e.g., only threshold
voltage on a 6T SRAM cell. Variation Designer's High Sigma brings
these techniques to bear using a large number of input variables
across a broad range of circuits.
- [ An Anon Engineer ]
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Solido looks very interesting, particularly the sensitivity analysis and
ability to quickly find corners of interest.
"Corner" analysis itself is getting way out of control. I see Solido's
tool as a way of controlling the explosion in circuit simulation licenses
we will otherwise need. We plan to evaluate their tool.
- [ An Anon Engineer ]
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At DAC, Solido briefly showed me their variation analysis tool, including
PVT, Monte-Carlo and proximity variation analysis.
In general, Solido's tool is powerful for variation analysis at the
transistor level. It includes the general functions which can be used
by circuit designers for analyzing their designs under inter-die and
intra-die variations.
Their statistic results come from SPICE runs, so they are trustworthy
and can be easily applied for arbitrary designs. Their sensitivity
analysis against variations provides the feedback for parameter tuning.
Besides a variation analysis tool, I would also like to see a tool which
can automatically optimize the yield. After all, the manual tradeoff
between yield and performances is a tough job for complex designs
especially when variations become larger.
- [ An Anon Engineer ]
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Solido Variation Designer
Solido has various products. We only focused on Variation Designer Monte
Carlo and a bit of PVT corners. The tools guide you in reducing number
of simulations that need to be done.
When you have a lot of variables (e.g. devices and corners), you need to
find separate experiments that vary the right ones to cover the right
design space without running a huge number of simulations. With regards
to their PVT Corner product, Solido uses the 'Design of Experiments' as
part of their sampling method to do this.
It's one thing to quickly generate a bunch of data, but without a way to
analyze the data in an efficient way, it's meaningless. It uses a lot of
GUIs, and Solido's reports were laid out well. Solido gives histograms
and scatterplots, then you can select an outlier and do further analysis
around that data point.
You can set different metrics and parameters - e.g. speed, threshold
voltage. The goal is to take Solido results and figure out that you
can't use a length and a width greater than a certain values for this
transistor because it puts it outside your specification.
- [ An Anon Engineer ]
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Solido: you can run Monte Carlo random analysis (e.g. with HSPICE) to
look at the constraint edges for your design, but for design covering
3 sigma (i.e. most designs), it is very time consuming requiring many
thousand simulations. For larger designs or when you need to design
to 4, 5, 6 sigma you may never be able to finish analysis; sspecially
since as design nodes get smaller, 2nd and 3rd order effects become
greater factors and the number of corners increases. This is where
Solido fits in.
'Variation Designer' analyzes your design for PVT (process, voltage,
temperature), including local and global variations. There are an
extremely large number of corners in the design space, and Solido
statistically extracts the corners to allow you to verify your design
at the constraint edges.
Solido is not a simulator but can be viewed as a simulation environment.
You use it with HSPICE or Spectre or FineSim or whatever.
Solido presents the analysis results in usable form. It tells you
the design sensitivity, and points you in the direction of the
sensitive transistors to look at. It guides you, but you have to
make the actual decisions on what to change. This tool does NOT
magically turn an inept designer into a good designer.
- [ An Anon Engineer ]
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I only took a quick look at Solido's Variation Designer presentation
at DAC, so I can only say a little about the tool.
I liked their fast Monte-Carlo analysis with automatic computation of
confidence intervals. Computing the confidence intervals without
Gaussian assumptions on the probability distributions was a interesting
and potentially useful approach. It's speed and GUI looked good, too,
but then again this was a demo.
- [ An Anon Engineer ]
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From Solido's DAC demo it seems that Solido's Variation Designer has
been able to reduce the number of simulation runs required for studying
the process variation issue.
The tool also can directly work with other commercial simulator such as
Cadence Spectre. The customer does not need to purchase a new simulation
tool. However, I do not have any hands-on experience on this tool to
verify the vendor's claim.
- [ An Anon Engineer ]
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Solido DA, Variation Designer:
Variation Designer looked promising for variation aware analog design by
delivering methods of reducing corners / the number of iteration needed
for running Monte-Carlo simulation. Having good integraton with Virtuoso
and fancy GUI delivering valuable information for designers were also the
strong point of Variation Designer.
- [ An Anon Engineer ]
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Solido is shifting from automatic sizing, and instead focuses on speeding
up Monte Carlos runs. They reveal the tradeoff of design parameters and
their impact on various performance specs.
- Weikai Sun of Tabula
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