( DAC 10 Item 4 ) ---------------------------------------------- [ 09/02/10 ]
Subject: Oasys RealTime Designer vs. Synopsys
POISED FOR TAKEOFF: This is the 2nd year that Oasys wowed the RTL synthesis
crowd at DAC, and the company is at a tipping point. Oasys needs to start
producing hands-on customers to do PUBLIC in-depth, meaty, technical tool
reviews validating that RealTime Designer is actually production ready
"real", just like Atoptech did in ESNUG 473 #1, AutoESL in 482 #6, Cadence
C-to-Silicon in 480 #5, Calibre nmDRC in 482 #3, Mentor Catapult C 477 #3,
Ciranova 473 #4, Extreme GoldTime 479 #2, EVE Zebu 483 #10, Gidel 486 #6,
IC Manage 482 #10, Magma FineSim 481 #6, Magma Hydra 483 #9, NextOp 484 #1,
Nusym 479 #5, PrimeTime 477 #2, PrimeTime SI 473 #2, Magma Quartz 483 #2,
Apache Redhawk 476 #6, Solido 485 #7, Synfora PICO 483 #4, Magma Talus
479 #6, Magma Titan 480 #4, and Mentor Veloce 482 #7.
If Oasys can do this, by next DAC they could be a viable $$$ threat to
the Design Compiler franchise.
"What were the 3 or 4 most INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?"
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Oasys Synthesis tool - Claiming to be 60X than Design Compiler. That
is amazing. Also can do the synthesis in less memory like in a laptop.
- [ An Anon Engineer ]
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Oasys showed release 9.3 which had support for VHDL, multi-mode (as
in the chip can operate in two different modes), System Verilog for
9/10. Roadmap for DFT and low power.
Their demo was a live run of a SPARC T1 design, 1.4 million instances,
1.2 Ghz, synthesizing to the Nangate 40 nm lib, on a Dell laptop with
an Intel dual-core 2.6 Ghz processor. The run took 22 minutes for
RTL-to-placed-gates. Impressive!
- [ An Anon Engineer ]
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I first looked at Oasys RealTime Designer at DAC in 2009 but didn't have
resources to look at it until this year. My feedback is based on Oasys'
claims - we are just getting started with our evaluation, so I don't
have hard data to provide yet.
Fundamentally, RealTime Designer (RTD) does ultra fast physical synthesis
on very large designs. It's disruptive technology in the synthesis world
because the speed is off the charts, while quality doesn't suffer. RTD
appears to use a "divide & conquer approach", it organizes your design's
logic into small groups, then places and optimizes each group for timing,
area, power, and routing congestion. It looks at the distance between
the logic groups and uses the wire length/capacitance for timing
optimization. Also, the tool is graphical so you can see the routing
congestion after placement. You can make floorplan adjustments and
re-synthesize again.
RealTime Designer has its own macro placer to provide physical designers
with a good initial seed on macro placement. If you don't have an
initial floorplan, it will optimize macro placement (memories) and the
rest of your design.
If you want to let RealTime Designer do it all, you can just feed it your
Verilog or VHDL RTL netlist and it gives you a good starting floorplan,
which saves you a lot of time consuming floorplanning iterations. If RTD
meets your target, you can just use the results. If you have additional
restrictions such as packaging, IR drop, and/or other IPs, you can
massage the floorplan yourself afterward. This is not hard to do, e.g.
you can place the IPs yourself and feed that floorplan to RTD, and it
will optimize your soft macro placement.
In a traditional design flow, you give the netlist to a place and route
engineer, and the engineer first creates a floorplan by placing macros,
I/Os, and IPs, etc. Once his floorplan is complete, then he gets his
P&R tool to optimize your design based on the floorplan and timing and
legalize the standard cells placement. Each of these steps have multiple
iterations for timing, congestion, etc. -- a lot of it is simply trial
and error. Oasys does this all in one shot.
By reducing synthesis and floorplan time, Oasys RealTime Designer could
give us more time to optimize our design and physical implementation.
RTD would also give our designers more opportunity to do "what if"
analysis in physical architecture, power, and physical implementation.
For example, we could potentially evaluate whether implementing our
design in 5 layer metal versus 8 layer metal would give us a more cost
effective design or not.
As part of our eval, we want to verify how good RTD's placement is. If
the tool does what Oasys claims, my goal is to reduce our engineering
resources by 50% and reduce our synthesis runtime by 50%. It could
potentially replace our current physical synthesis flow.
Not only could Oasys be a nightmare for Synopsys, but also for Cadence RC
Compiler and for Mentor Olympus.
- [ An Anon Engineer ]
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Oasys' ability to take a million instance design in less than 25 minutes
from RTL-to-placed-gates is very impressive. From their DAC demo, it
appears Oasys Realtime Designer hands down beats DC-Topo in terms of
runtime performance & memory footprint without compromising on QoR.
Also, I was impressed with the RealTime's ability to cross probe between
RTL/netlist & physical placement throughout the flow. This is key for
proper communication between the RTL team and the implementation team.
- [ An Anon Engineer ]
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Oasys is intriguing. They are doing something that the industry hasn't
been doing. Based on what I saw in their DAC demo, RealTime Designer
analyzes your code structure before jumping down to the gate level.
Because they make high level architectural choices before synthesis, they
can get a smaller footprint and couple in more placement-awareness into
your chip for a better result. Synopsys DC-Graphical and DC-Topo are
trying to do this, but Oasys has architected it from a clean start.
- [ An Anon Engineer ]
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Oasys RealTime is quite amazing in their extremely short run time, and
large capacity. I was reluctant to look into this technology initially
because the existing momentum with the synthesis technology currently
available. But Oasys definitely can have a voice in this area if the
cards are played correctly.
Their drawback is lack of DFT support, and having a good relationship
with a company that produces logic equivalence checking tool (the two
major EC tool are owned by their main competitors, Synopsys and Cadence).
Regardless I am still positively impressed by their technology after
going through it at DAC.
- [ An Anon Engineer ]
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Most interesting:
Oasys - Has a tool that can do chip synthesis much faster, with higher
quality and capacity than Design Compiler. Oasys' tool is innovative
in two ways:
(1) They do placement during the RTL elaboration stage, thereby
solving the classic chicken-egg problem of doing optimization
without knowing what physical implementation might look like.
(2) They have a method to abstract timing early in the synthesis
process using that placement, but without weighing down the
synthesis process with time consuming details of placement or
taxing "what-if" banana curve experiments with heavy placement
databases full of details that are irrelevant to early
synthesis optimizations.
The result -- Oasys is fast -- really fast -- and "wires" accurate. What
took 20 hours in DC, maybe 10 in RC Compiler, takes ~1 hour in RealTime.
RealTime is innovative compared to the Synopsys/Cadence/Mentor/Magma
physical synthesis solutions, which are essentially an automated handoff
between traditional synthesis and placement that seems to result in
infinite run times over 1M instances. Oasys also handily beats the newer
"enlightened" wire load model fixes, where the synthesis tool tries to
estimate timing by studying the LEF (aka RC-PLE, DC-T). In my experience,
these tools are only marginally better than WLMs because they don't
compute physical location, often poorly predicting actual P&R results.
Credit to some new SPNS/CDNS synthesis innovations which study the DEF
and make an effort to solve the long-wire/non-square synthesis floorplan
problem without placement (RC-Physical, DC-G), but in my opinion, Oasys
has developed the "holy grail" that Synopsys & Cadence have been
searching for since the PKS days. RealTime does a synthesis seeded by
real wires derived from placement, but which does not have the runtime
hit of physical synthesis, yet, you can actually close timing and
legalize the placement.
Oasys can push a netlist and floorplan to the backend to finalize. They
have 3 key advantages:
(1) Their tool is so fast that chip designers can do quick
exploration and make better high level tradeoffs.
(2) Their capacity to meet the demands of chip integrators facing
100M gate designs or greater in coming years.
(3) Oasys enables simultaneous floorplan refinement alongside
synthesis -- an innovation that will likely close the gap
between the frontend and backend designer, speeding overall
development time; the Berlin Wall of EDA continues to fall.
Oasys is a young, innovative company. They not been sitting still.
This is the second year I have attended their demo and they have several
customers now and have added CPF support, hierarchy, and multithreading
to their tools. Oasys challenge is to beat down entrenched competitors
like Synopsys and Cadence while making the investments necessary to
partner with customers to refine and mature their technology while
weathering the downturn. If Oasys can navigate these hazzards and
execute, their technology will change the game, make engineers more
productive, while improving the quality of the chips going out the door.
It will be interesting to see how it plays out.
- [ An Anon Engineer ]
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I have been very impressed with Oasys' tool! They are allowing logic
designers to get highly predictable and optimized results in less time
than it takes for 1 Design Compiler run without placement!
- [ An Anon Engineer ]
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Oasys have matured their tool and truly its an innovative product. For
example, the ability to visualize the critical path in the RTL (yes RTL)
after placement is amazing. This is the kind of functionality that users
want so that timing can be fixed earlier in the design cycle. IMO the
company has vision, expertise, and a bright future.
- Himanshu Bhatnagar of Mindspeed Technologies
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The best tool that drew my attension and I am very enthustiastic about it
is "Oasys", addressing BIG designs and best QOR for physical synthesis
in a new way (not the old where DC/Magma get stuck with elaborated RTL or
Gtech format and keep pounding on it for the rest of synthesis steps).
- [ An Anon Engineer ]
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Oasys - RealTime Designer
Nice to see that Oasys RealTime Designer is now real and in production.
This product still seems like a "game changer."
- [ An Anon Engineer ]
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