( DAC 10 Item 10 ) --------------------------------------------- [ 11/19/10 ]
Subject: Magma Titan vs. Cadence Virtuoso
DAVID VS. GOLIATH: While Synopsys likes to pretend that its Custom Designer
tool will crush Virtuoso's iron grip on the full custom market, it appears
Magma Titan is what's getting some traction in the user base. SpringSoft's
Laker is much older than Titan, but I haven't heard of any big name users of
it outside of Taiwan. VPAD seems to be Cadence's response to Magma's Titan.
Now designers have to choose between lots of automation or lots of control.
"What were the 3 or 4 most INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?"
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Magma Titan
I knew from your old Wiretap back in 2007 that Magma had purchased code
from Stabie-Soft (see http://www.deepchip.com/wiretap/070620.html), but
in the Magma Titan DAC demo, it was apparent that while Magma did a lot
of work on it, Titan is in fact basically Stabie-Soft. This gives Titan
instant credibility with me. If Mike Stabenfeldt spent 10 years on it,
it's good.
- John McGehee of Voom, Inc.
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Magma sells Titan which is used for chip finishing and they emphasize
it is tightly integrated with their Quartz DRC/LVS and FineSim SPICE.
There is a path to translate Pcells for their tool; Synopsys has a
couple of gurus who translate Pcells to Py-cells, which is not for
amateurs. I suspect as iPDKs become more available from more
foundries (thanks in large part to pressure from Synopsys) they will
start to complete more with Cadence Virtuoso. Titan can use SKILL
based PCELLs if the user has a Virtuoso license; I'm not sure of the
details.
They have a shape based router, Titan SBR, which competes against
Pulsic and Cadence Catena. Magma said theirs is the only timing-driven
shape-based router and is great for chip level routes that need
co-axial shielding, etc.
Their Titan AVP tool (analog virtual prototyping) tool provides early
area estimates and fast early parasitics for early simulation. Their
Titan ALX tool facilitates fast process migration (layout in, layout
to new design rules out). They say that for one customer, migrating
a SERDES went from 16 months to 1 day (your results may vary).
They also have a tool called Titan ADX, which does transistor sizing
(netlist to sized netlist). It uses a "circuit template" entered in
a MATLAB style language. Sizing is equation based (not Monte Carlo).
They provide equations for common building blocks (op amp, bandgap,
etc.) based on public information, and the user can verify these with
SPICE and modify them if needed.
- John Weiland of Abraxas Corp.
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I attended two Magma demos during DAC 2010:
Titan: Enabling Analog Design Reuse, and
Titan: Automatic Process Migration for Analog Designs
According to Magma, Titan is the first industry platform "which provides
a truly integrated environment for design and verification of
analog/mixed-signal circuits."
Magma currently offers four Titan Accelerators:
Analog Design Accelerator (ADX)
Analog Virtual Prototyper (AVP)
Analog Layout Accelerator (ALX)
Shape-Based Router (SBR)
The two demos I attended covered ADX and ALX accelerators. I gathered
that users do not necessarily need to have Titan to use these two
accelerators as they can be integrated into various platforms such as
Cadence Virtuoso.
Session #1: Enabling Analog Design Reuse
This covered Titan Analog Design Accelerator (ADX). This accelerator
aims at optimizing analog circuits, design reuse, and migration.
- ADX comes with a library of most-commonly used circuit topologies,
e.g. different types of op-amp, current mirrors, etc. These are
called FlexCells and serve as building blocks of designs and are
process-independent. FlexCells are written in MATLAB format and
based on what I understood they include particular circuit models,
design constraints, and layout floor plans.
- To do optimization, first ADX looks at the existing circuit and
tries to identify different parts of the circuit by referring to
the collection of available FlexCells. Once this is step is done,
using the info provided by relevant FlexCells, corresponding
process-independent equation-based circuit models are generated.
Then these models in conjunction with data from SPICE/Spectre
models are passed to an optimization engine for optimization. The
results can be produced in MATLAB-ready and ASCII formats.
From this step, ADX does what most other optimization tools do: they show
you sensitive devices, which specs are failed, what corners are most
crucial, how to fix, etc.
One thing which I liked about this methodology is that designers can
write their own FlexCells. You can do non-common circuit topologies.
A designer can virtually introduce any type of design constraints in
FlexCell files by writing the corresponding mathematical equations and
have the ADX optimization engine to figure out possible solutions.
The other point I liked is that FlexCells are process-independent. As
a result default and custom FlexCells can be readily used in different
technologies with not many modifications. Particularly useful for
schematic migration.
I did not see exactly how layout floor plan information in FlexCells
could be used, but I guess another Titan Accelerator would use them to
automatically generate layout from schematic. I don't know for sure.
Session #2: Automatic Process Migration for Analog Designs
This covered Titan Analog Layout Accelerator (ALX). The presenter went
over layout migration of a design which had been created by one of
Magma's customers. What was provided by the customer:
-design netlist for the original technology
-design layout for the original technology
-design netlist in the target technology
In this demo, it took only a few minutes for ALX to generate a migrated
layout in the target technology. Stuff they highlighted:
- ALX generates DRC/DFM clean layouts
- ALX identifies analog-related properties in the original
layout, e.g. matching, alignment, symmetry and preserves
them in the target layout
- ALX identifies PCells in the original layout and in the
target layout and replaces them with PCells from target PDK
- ALX "reduces migration time from weeks and months to hours"
In addition to layout migration, they claim that ALX can be used to
modify or optimize a current layout very quickly.
Magma's recommended way to perform a complete project migration was to
use ADX to migrate schematics, and then use ALX to migrate layout using
your original netlist/layout and ported netlist created by ADX.
- [ An Anon Engineer ]
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2. Titan Platform - Magma
a. First the optimization engines from Sabio/Barcelona with the help
of AVP placer from Accelicon are providing a transistor level
optimization based on real placement and virtual or real routed
design in seconds. Design and layout architecture of analog design
will never be the same for any circuits. Even if the solution is
not the perfect one, the user can achieve 80% of the job in one day
with 90% accuracy of process in LOD and WPE time. This is a real
breakthrough! You can get the real device size based on your
placement within the Nwell. Some call it "real LVS". The layout
device size is the expected simulated value *after* manufacturing;
not the size drawn in layout. (Two devices that are supposed to be
same size will have different sizes after manufacturing based on
their relative position to well edge and other topologies.)
- [ An Anon Engineer ]
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Don't get me wrong, the Titan ADX presentation was awesome. The tools
look great and they look like every circuit designers dream. To be able
to bring up your schematics, add some constraints and presto... you have
layout. They did look good, they looked great. On many many occasions
the Magma presenter repeated himself assuring his audience that this tool
can create that layout in hours, minutes, compared to "those" layout
designer with rival tools that take weeks. It is design rule correct,
aligned, placed, matched, and DRC clean. It really did look great...
except for one thing... I am a layout designer.
We asked a few questions, and, due to the world of DAC presentations and
the lack of real time designs that can actually be manipulated at DAC,
we were assured the tool could do it -- but it was not possible to show
us it, at that time.
- [ An Anon Engineer ]
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What is the Cadence answer to Magma Titan automated "analog synthesis
and optimization"?
A flow that enables the user to make decisions at every step based on
info coming from a processing called "Virtuoso In-Design DFM" or
VPAD (Virtuoso Parasitic Aware Designer).
1. First the designer enters known and "wished" constraints for
implementation. If none, the VPAD can do some initial
estimation from process and PCELL data.
2. The tool can come back and tell what is possible or not and
where the design is "over constrained" -- thus helping
designers to do a first level of circuit optimization.
3. On the implementation stage, placement and routing of all the
constraints are followed with MODGEN and router. Your more
important electrical constraints can be defined and followed.
If P&R not possible, the verification of constraints can show
what cannot be achieved. If a user breaks something, the
checked design can be called back to verify adherence to
requests.
VPAD differences from Titan:
1. CDNS assisted flow is not a fully push button philosophy. The
designer is involved at every step. This can be good or bad
depending on your desire for control or for automation.
2. VPAD allows user to evaluate at all stages.
3. If broken, VPAD performs re-checks of constraints.
VPAD differences to Ciranova:
1. All VPAD data is integrated including routing and MODGEN
with hierarchically smart Pcells.
2. VPAD has knowledge of all post-layout process simulation.
3. VPAD can re-check constraints in design as well as in layout
if they're manually broken (which is very often the case).
So if Magma Titan is the "automated" full custom analog flow, Cadence
VPAD is the "assisted" solution... Now just wait for 6.15 to get all
of these actually working on your workstation.
- [ An Anon Engineer ]
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Cadence's Virtuoso suite is the dominant tool in the analog/RF/custom
market. In order to do designs like these one needs a Physical Design
Kit (PDK) from the foundry. The descriptions of transistors and other
basic components are usually via Cadence's proprietary P-Cells, which
has given Virtuoso a monopoly for years. As Open Access (OA) PDKs
become more available, there may be more competition.
The basic L of Virtuoso version allows distributed simulation, the XL
version allows specification driven design, and the GXL version does
automatic generation of .lib models and has connections to the Allegro
SiP (System in Package) design tool. Their Analog Design Environment
(ADE) ties in simulation, either their Spectre or 3rd party simulators
like HSPICE. The XL version of ADS supports multiple tests and corner
analysis, and the GXL version adds parasitic analysis, characterization,
design centering and yield optimization.
Virtuoso also has an AMS Designer option to support mixed design and
simulation.
Cadence sells the older Virtuoso Chip Assembly Router (VCAR) and the
new Space-Based Router. Both are designed for automation of custom
routing. The newer product has higher capacity and a larger price tag.
Cadence has an AMS Methodology Kit and an RF Design Methodology Kit
with good examples and scripts and both are now free (they used to
cost big bucks).
Ciranova has been giving away "Py-Cell Studio" for a while, so that the
world would have an alternative to Cadence P-Cells. Their Py-Cells are
now the standard for interoperable Physical Design Kits, which are
available from TSMC and Tower as an alternative to Cadence-specific
PDKs. Now that Py-Cells are taking off, Ciranova can sell their real
product. Their Helix tool (not to be confused with the Greek company
Helic) is a fully automated floorplanner, placer and router for analog
design. At the moment they call it "trial routing" (the user may need
to modify it) but emphasize that good placement makes analog routing
easier. The input to Helix is a SPICE netlist, a cell library, tech
file (best results if it uses Py-Cells because the tool can vary the
parameters) and constraints (either from a GUI or a file in their own
format). The output is multiple Open Access layouts with different
aspect ratios. Ciranova emphasize that their tool makes technology
migration easy because the design constraints are saved. They say
Cambridge Silicon Radio (CSR) is a major customer.
SpringSoft makes Laker, a long time competitor to Virtuoso. They claim
Laker's schematic-driven layout capability works better than Virtuoso's.
They say it has a "rule cognizant" cross hierarchical environment with
automatic sizing, placement and routing, automatic schematic generation
and layouts that are automatically DRC clean. They can also do autoroute
of the digital portion of AMS designs. They say their M-Cells are
simpler and faster than P-cells. TSMC now provides some PDKs that
support Laker. Otherwise they create their own PDKs and selection is
limited; for example, they do not support IBM.
- John Weiland of Abraxas Corp.
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Laker + Calibre on OA - Springsoft and Mentor working together to
enable full signoff DRC check in a DRD style environment. Calibre
run in seconds in the background every time you unselect a polygon
in Laker based on layer. When layout is complete it's 100% DRC clean.
- [ An Anon Engineer ]
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* mixed-signal P&R solution - Cadence
* oPDK standardization
* power transistor RC Extraction and Analyses - Silicon Frontline
- Thomas Ramsch of X-Fab GmbH
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